Dynamic Random Access Memory Data Research Articles

A Performance Evaluation of DRAM Access for In-Memory Databases

The latest CPUs(computer cpu processors) employ multiple cores, massively superscalar pipelines, out-of-order execution of tons of instructions, and advanced SIMD capabilities, which can hide the memory access latency. And most of recent memory-oriented data structures have already benefit from these features. However, due to the complexity of data organization, these CPUs do not always work well in memory resident database systems (MMDBs), particularly regarding storing data in dynamic random-access memory (DRAM). This article studies memory-efficient data structures by analyzing the run time, access latency, cache misses, instructions per cycle (IPC), and DRAM reads (bytes). Then, we design and implement two data organization schemas in the main memory database: dispersing data block organization and clustering data block organization. Using algorithmic engineering and careful attention to internal parallelism, cache alignment can hide the memory access latency. However, we find that these data structures work well in some cases, though they have been eclipsed in the face of complex access paths. To determine the reasons, we study the impact of database techniques on memory access latency, such as data partitioning, storage models, and by processing algorithms. With the specific main memory database system, we estimate the performance of each data organization schema based on DRAM DDR4 and the latest Intel Haswell microarchitecture. In conclusion, this work will make DRAM access applicable in real-world situations by implementing the schema to systems, such as in-memory databases.

Reliability of Hybrid Supercapacitor for Persistent Memory Application

Supercapacitor technology is able to bridge the application gap between chemical batteries and conventional capacitors. Supercapacitors possess a higher energy density than capacitors and a higher power density than electrochemical batteries. The quick charge/discharge ability and long cycle life makes them reliable and applicable where power bursts are required. In efforts to avoid data loss in critical computer applications, such as defense-related, banking, healthcare, etc., persistent memory was created. Persistent memory utilizes backup power from a battery to retain data in Dynamic Random-Access Memory (DRAM) long enough for the data to be transferred to the non-volatile flash in case of a power interruption. To identify failure modes, different reliability tests were performed on the Backup Power Module (BPM): Temperature, Humidity, Bias test, the shelf life test, the cycling test, and the accelerated aging test. From these reliability tests, it was observed that when there is variation in potential across individual cells in the pack, it will accelerate the aging of all the cells connected in series. Also, the cycling test gave an indication of reducing charge/discharge time when cycles were extended beyond the predefined cycle test count. An experimental design is suggested for future work that varies temperatures and voltages, with the response variable being the ability of a supercapacitor to hold charge in a prolonged cycling test. As a result of these reliability assays, it was determined that a major reliability concern was traced to a manufacturing process and a suggestion for the improving a manufacturing step is made.

UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer Cache

Journaling techniques play an important role in addressing the reliability issue of filesystems caused by the volatile dynamic random access memory (DRAM)-based buffer cache. However, journaling techniques introduce a large number of extra storage writes, which greatly degrades system performance, especially for mobile devices. Emerging nonvolatile memory (NVM) technologies bring a new perspective of solving the write amplification issue caused by journaling. By adopting NVM as the buffer cache, the committed data can be maintained in NVM before being written back to the storage, thus, eliminating the journaling overhead. However, simply utilizing NVM as the buffer cache suffers from the limited lifetime and the relatively longer write latency of NVM. In this paper, we present a hybrid buffer cache architecture, named UniBuffer, by combing NVM with dynamic random access memory (DRAM) to reduce the journaling overhead and overcome the inherent constraints of NVM. In UniBuffer, we first propose a journaling-aware page management (JAPM) policy to smartly allocate data to DRAM and NVM pages. JAPM puts infrequently updated data in NVM to reduce the journaling overhead and frequently updated data in DRAM to improve the write performance and lifetime of the hybrid buffer cache. In addition, since data in one journaling transaction may be dispersed in NVM and DRAM simultaneously, different committing policies are required for different storage media, respectively. In order to guarantee the atomicity of the transaction execution in the hybrid cache architecture, a partial in-place commit (PIPC) journaling scheme is proposed to coordinate different committing patterns for NVM and DRAM. We have implemented the proposed techniques on Linux 3.14.52 and measured the performance with representative I/O-intensive benchmarks. The experimental results show that our scheme effectively improves the I/O performance compared with the ext4 filesystem and prolongs the lifetime of the hybrid buffer cache compared with the union of buffer cache and journaling (UBJ) scheme.

Nonblocking DRAM Refresh

Since its invention half a century ago, dynamic random access memory (DRAM) has required dynamic refresh operations that block read accesses to refreshing data; this fundamental behavior gave DRAM its name. In contrast, DRAM's close relative—static random access memory (SRAM)—can statically re-enforce charge in the background without blocking read accesses at the cost of more expensive circuit structure. Nonblocking DRAM Refresh blurs this fundamental distinction between DRAM and SRAM at the system level to enable the best of both worlds—allowing read accesses to refreshing data in DRAM while preserving DRAM's low-cost circuit structure.

A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems

Dynamic random access memory (DRAM) reliability has become one of the critical issues in embedded systems, as DRAM process technology advances with the increase in bit error probability. Unfortunately, redundant error-correction code (ECC) chips cannot be applied to embedded systems since cores and DRAMs are tightly coupled without a dual in-line memory module (DIMM) slot to account for the form factor, cost, and limited pin count. Therefore, ECC parities are typically placed in the same physical array where the user and system data reside. This coexistence eventually deteriorates data locality, which could be the critical factor in DRAM performance degradation. To address this issue, we propose an ECC scheme called locality-aware compression (LoComp) which integrates a compression algorithm, DRAM data layout, and memory controller especially optimized for embedded systems. We focus on the locality of the dataset and its corresponding metadata, as well as spatial data locality in the design of DRAM data layout, which reduces the number of row activations. The major feature in a compression algorithm is adjusting the misalignment of data streams caused by the data packing in many embedded systems. Moreover, we specialize the memory controller to reduce DRAM access for ECC parities and compression flags. The core technologies for the memory controller are the adoption of a set of small caches for metadata and the support of partial write operation without changing the DRAM interface. LoComp+, an enhanced version of LoComp, further reduces DRAM access for metadata by placing the metadata close to the corresponding data. In the experiment, previous works increase the DRAM access time from 68% to over twice the value compared to ECC DIMM. Whereas, LoComp and LoComp+ show reduced performance degradation by 33% and 48%, respectively. In other words, LoComp and LoComp+ substantially improved performance from between 13% and 33% compared to previous embedded ECC schemes.

Dynamic Adaptive Replacement Policy in Shared Last-Level Cache of DRAM/PCM Hybrid Memory for Big Data Storage

The increasing demand on the main memory capacity is one of the main big data challenges. Dynamic random access memory (DRAM) does not represent the best choice for a main memory, due to high power consumption and low density. However, the nonvolatile memory, such as the phase-change memory (PCM), represents an additional choice because of the low power consumption and high-density characteristic. Nevertheless, the high access latency and limited write endurance have disabled the PCM to replace the DRAM currently. Therefore, a hybrid memory, which combines both the DRAM and the PCM, has become a good alternative to the traditional DRAM memory. Both DRAM and PCM disadvantages are challenges for the hybrid memory. In this paper, a dynamic adaptive replacement policy (DARP) in the shared last-level cache for the DRAM/PCM hybrid main memory is proposed. The DARP distinguishes the cache data into the PCM data and the DRAM data, then, the algorithm adopts different replacement policies for each data type. Specifically, for the PCM data, the least recently used (LRU) replacement policy is adopted, and for the DRAM data, the DARP is employed according to the process behavior. Experimental results have shown that the DARP improved the memory access efficiency by 25.4%.

Residual Clamping Force and Dynamic Random Access Memory Data Retention Improved by Gate Tungsten Etch Dechucking Condition in a Bipolar Electrostatic Chuck

Residual Clamping Force and Dynamic Random Access Memory Data Retention Improved by Gate Tungsten Etch Dechucking Condition in a Bipolar Electrostatic Chuck

Residual Clamping Force and Dynamic Random Access Memory Data Retention Improved by Gate Tungsten Etch Dechucking Condition in a Bipolar Electrostatic Chuck

It was found that the residual clamping force of bipolar electrostatic chucks created by the residual charge between a wafer and an electrode would not only cause a wafer sticking problem but also degrade dynamic random access memory (DRAM) data retention performance. The residual clamping force and data retention fail bit count (FBC) of DRAM showed strong correlations to the gate tungsten etch dechucking process condition. Wafer sticking only degraded DRAM cell retention performance, and did not influence any in-line measurement or electrical parameters. Electrical characterization analysis of the FBC proved that the retention loss was mainly due to junction leakage rather than gate-induced-drain-leakage current. A new approach was proposed to suppress this leakage by introducing N2 gas instead of O2 to supply more plasma charges for neutralizing the wafer surface residual charges. The wafer shift dynamic alignment (DA) offset and retention FBC could be reduced by 50 and 40%, respectively. Poor data retention was suspected because of the compressive stress caused by wafer sticking DA shift resulting in a high electric field at the junction and an increase in junction leakage at the storage node.

DRAM Data Retention and Cell Transistor Threshold Voltage Reliability Improved by Passivation Annealing Prior to the Deposition of Plasma Nitride Layer

We report, for the first time, that the fail bit counts of dynamic random access memory (DRAM) reduced by 18% and the yield loss after packaging induced by data retention degradation decreased by 1.16% for a trench DRAM cell; this reduction was attributed to a change in the process position of passivation annealing. Moreover, the cell transistor threshold voltage (CTVth) shift was reduced to 53 mV, and the uniformity of the CTVth was improved from 100 to 38 mV; this provided the DRAM cell with a large margin for further reducing both the dose of the threshold implant and the electrical field. We proposed a possible mechanism of carrying out passivation annealing prior to the deposition of a plasma nitride layer in order to increase the supply of hydrogen for the passivation of the crystalline defects as well as improving data retention. The CTVth was increased by breaking of weak Si-H bonds by plasma charging during the deposition of the plasma nitride layer. Data retention degradation after the packaging process ( ~ 250°C) reduced because of the presence of a number of strong Si-H bonds, indicating the presence of a greater number of interface trap states near the storage trench than near the bit line, as observed in the case when hot-carrier stress was applied under two conditions. Results of data retention analysis show that the fail bit counts are primarily influenced by the junction leakage current and not the gate-induced drain leakage current. Above observation is dependent on device process flow, which provided us an easy way for DRAM device optimization and maximized manufacturing process window.

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

We generated traps inside gate oxide in gate–drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler–Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal–oxide–semiconductor field-effect transistors (MOSFETs).

Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells

We have investigated the impact of gate etch post-cleaning process on the tail distribution of data retention time in dynamic random access memory (DRAM) cells having polymetal (W/WNx/Poly-Si) gate device based on the fully mature technology of sub-micron DRAM. In this paper, we propose the optimized gate etch post-cleaning condition in polymetal gate device to guarantee the characteristics of DRAM data retention time comparable to that of the conventional polycide (WSix/Poly-Si) gate etch post-cleaning process. In addition, for the first time, we have verified that the effective removal of the unwanted residue generated by gate etch improves the interface quality of the remaining oxide at the gate edge, resulting in improving the tail component of data retention time.

Field-effect trap-level-distribution model of dynamic random access memory data retention characteristics

Dynamic random access memory data retention characteristics were investigated as a function of operating voltage. Based on a statistical process, called the trap-level-distribution model, which was proposed in our previous report, we further assumed that the junction leakage current by Shockley–Read–Hall process is enhanced by an electric field through the trap-assisted-tunneling process. We incorporated into the model two processes that cause variation in the electric field at the traps; the variation of electric field itself and the spatial trap distribution. By comparing the Monte Carlo and analytical calculations with the experimental results, we found that the retention time distribution is not only caused by the energy level and spatial distributions of the traps, but by the space-charge-region field distribution among the cells. A possible origin of the field distribution is the variation of dopant profile among the junctions.

Evaluation of micro-defects by DRAM data retention characteristics measurement

The influence of micro-defects induced intentionally by Si + ion implantation was investigated using data retention characteristics of dynamic random access memory (DRAM). The defect formation was controlled by Si + implantation and subsequent annealing conditions. Micro-defects such as {311} defects having a size below 50 nm degraded the junction leakage current and data retention characteristics. Data retention characteristics was also affected by the existence of micro-defects such as point defect or its clusters, although the junction leakage current was low enough compared with unimplanted samples.

Statistical modeling of dynamic random access memory data retention characteristics

A statistical model to investigate the distribution of dynamic random access memory data retention times is proposed. The model assumes that the retention time is determined by a junction leakage current generated at carrier traps by a Shockley–Read–Hall process, and that the trap levels are randomly distributed not only among the memory cells but also within a cell. Monte Carlo results based on the model were in excellent agreement with experimental results, which confirmed the validity of the model. An analytical expression of the retention time distribution was also derived, and proved a good approximation near the 50% cumulative probability. Based on the model, variation in the retention time distributions among samples was found to be related to different trap-level distributions at the SiO2/Si interface.