Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells

Abstract

We have investigated the impact of gate etch post-cleaning process on the tail distribution of data retention time in dynamic random access memory (DRAM) cells having polymetal (W/WNx/Poly-Si) gate device based on the fully mature technology of sub-micron DRAM. In this paper, we propose the optimized gate etch post-cleaning condition in polymetal gate device to guarantee the characteristics of DRAM data retention time comparable to that of the conventional polycide (WSix/Poly-Si) gate etch post-cleaning process. In addition, for the first time, we have verified that the effective removal of the unwanted residue generated by gate etch improves the interface quality of the remaining oxide at the gate edge, resulting in improving the tail component of data retention time.