DRAM Data Retention and Cell Transistor Threshold Voltage Reliability Improved by Passivation Annealing Prior to the Deposition of Plasma Nitride Layer

Abstract

We report, for the first time, that the fail bit counts of dynamic random access memory (DRAM) reduced by 18% and the yield loss after packaging induced by data retention degradation decreased by 1.16% for a trench DRAM cell; this reduction was attributed to a change in the process position of passivation annealing. Moreover, the cell transistor threshold voltage (CTVth) shift was reduced to 53 mV, and the uniformity of the CTVth was improved from 100 to 38 mV; this provided the DRAM cell with a large margin for further reducing both the dose of the threshold implant and the electrical field. We proposed a possible mechanism of carrying out passivation annealing prior to the deposition of a plasma nitride layer in order to increase the supply of hydrogen for the passivation of the crystalline defects as well as improving data retention. The CTVth was increased by breaking of weak Si-H bonds by plasma charging during the deposition of the plasma nitride layer. Data retention degradation after the packaging process ( ~ 250°C) reduced because of the presence of a number of strong Si-H bonds, indicating the presence of a greater number of interface trap states near the storage trench than near the bit line, as observed in the case when hot-carrier stress was applied under two conditions. Results of data retention analysis show that the fail bit counts are primarily influenced by the junction leakage current and not the gate-induced drain leakage current. Above observation is dependent on device process flow, which provided us an easy way for DRAM device optimization and maximized manufacturing process window.