Dynamic Latch-up Research Articles

A Refinement Multilevel Turn-off Method for Dynamic Latch-up and Tail Current Suppression in DC Breaker Ultra-High Current Switch Applications

A Refinement Multilevel Turn-off Method for Dynamic Latch-up and Tail Current Suppression in DC Breaker Ultra-High Current Switch Applications

Comparisons of Two Turn-off Failures Under Clamped Inductive Load in Planar FS 3.3 kV/50 A IGBT Chip

Turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> failure under clamped inductive load, is one of the most concerns in insulated gate bipolar transistor (IGBT) chips. Besides, this turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> failure can be attributed to two causes, i.e., the dynamic latch-up and the secondary breakdown. Despite great simulation work investigated previously, the experimental research should be further focused. Up to now, the typical features and differences for these two turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> failures still remain unclear. In this article, two failures’ waveforms are first compared in experiment. Moreover, their internal current, electric field, and temperature distributions are compared by simulation in detail. Then, two different failure features, focusing on the failure cell structures, are summarized from the scanning electron microscope (SEM) results for the first time. The marked signatures of these failures, such as the current filament path and the mixture region, are further analyzed in this article. According to the SEM results, the lateral and vertical current paths can be observed in dynamic latch-up chip and secondary breakdown chip, respectively. These failure signatures in waveforms and SEM results can contribute to the distinguished method to the failure causes in IGBT device, and enhance the chip's performance more effectively.

Simulation Study of Overcurrent Turn-off Capability in 4500V IGBT

According to the requirement of IGBT's over-current turn-off capability, this paper analyzes the factors affecting the dynamic latch-up of IGBT chip during the over-current turn-off process, including the gate width of IGBT cell, the doping concentration of back P + collector and the dVce/dt when the IGBT is turned off. The simulation results show that the anti-dynamic latch-up capability of IGBT can be effectively improved by decreasing the gate width and back P + collector doping concentration. Through multi-cell parallel simulation, it is found that current concentration exists in the process of overcurrent trun-off, which leads to the further increase of the lattice temperature, and the overcurrent turn-off capability declines.

Distributed electro-thermal model of IGBT chip – Application to top-metal ageing effects in short circuit conditions

A new distributed electro-thermal model has been developed in order to analyze electrical and thermal mappings of power devices during critical operations. The model is based on dividing power device into a vertical multilayer structure, with each layer discretized into multiple slab volumes. This model has been used to evaluate the effects of chip metallization ageing on temperature distributions and current sharing between cells within an IGBT chip during short-circuits operations. Dynamic latch-up failures during short-circuit operations has been investigated.

On the reliability assessment of trench fieldstop IGBT under atmospheric neutron spectrum

In the early 1990s, active power devices have been shown to be susceptible to radiation-induced failures. Many studies have been focused on cosmic ray-induced power device failures, including even IGBT failures. Till the end of the 1990s, IGBT technologies were susceptible to static or dynamic latch-up, which are respectively occurring in their forward conduction or switching mode. From then on, new technologies, such as trench gate fieldstop IGBTs providing significant improvement in the latching current capability, have been developed. But so far, the impact of atmospheric radiation has not been assessed on actual technologies. With the expected increase of embedded IGBTs in avionics and automotive applications, the impact of neutrons on the functional security of embedded systems has to be quantified.

Advanced SPICE Modeling of Large Power IGBT Modules

An enhanced insulated gate bipolar transistor (IGBT) model based on the Kraus model with new derivations based on an extra parameter accounting for p-i-n injection was developed to allow simulation of both trench and DMOS IGBT structures. Temperature dependence was also implemented in the model. The model was validated against steady-state and transient measurements done on an 800-A 1.7-kV Dynex IGBT module at 25/spl deg/C and 125/spl deg/C. The Spice model has also shown excellent agreement with mixed mode MEDICI simulations. The Spice model also takes into account for the first time the parasitic thyristor effect allowing the dc and dynamic temperature-dependent latchup modeling of power modules as well as their temperature-dependent safe operating area.

Dynamic latch-up in advanced LIGBT structures at high operating temperatures

Abstract The dynamic latch-up process in conventional and modified lateral insulated gate bipolar transistor (LIGBT) structures is studied in this paper. In a previous study, we have argued that the modified structure shows a superior static latch-up performance at high operating temperatures. The dynamic latch-up has also been measured under resistive load at different operating temperatures. The dependence of the dynamic latch-up current with the gate resistance has also been taken into account. A figure of merit of the dynamic latch-up current normalized to the static latch-up current level as a function of operating temperature shows the excellent electrical behaviour of the proposed modified LIGBT structure at high temperatures when compared with its conventional counterpart.

A new lateral IGBT for high temperature operation

The analysis of a new LIGBT with special emphasis on high temperature behaviour is discussed. A comprehensive experimental characterisation of the static characteristics over the temperature range 300–423 K is reported. Two-dimensional (2-D) numerical simulations are used to explain the observed behaviour and to get a physical insight into the effects of temperature on LIGBT performance. Simulation results show a peculiar latch-up mechanism in the proposed new modified structure different from the conventional IGBT structure. The novel LIGBT structure, proposed here, has been compared with LIGBT structures previously reported. All these structures have been fabricated. The experimental latch-up current density of the proposed LIGBT is four times higher than in the other fabricated structures at high temperature. The dynamic latch-up during the LIGBT turn-off process has also been analysed.

Numerical analysis of temperature dependence of very-short-pulse-induced dynamic latchup in CMOS

The temperature dependence of very-short-pulse-induced dynamic latchup in CMOS is studied over a temperature range of 77–400 K through two-dimensional device simulation with fulltemperature models. When the trigger-pulse duration decreases below 10 ns the temperature dependence of latchup immunity comes to disagree with the results of previous other studies, showing that latchup immunity increases with decreasing temperature. For very short pulses latchup immunity decreases monotonously or has its local maximum value at about 120 K and then decreases as the temperature decreases. Pulse-induced dynamic latchup sensitivity at 77 K exceeds that at 300 K when the pulse duration becomes shorter than a certain very small value. This temperature dependence mechanism of very-short-pulse-induced latchup is discussed in detail.

The modified structure of the lateral IGBT on the SOI wafer for improving the dynamic latch-up characteristics

The modified structure of the lateral IGBT(LIGBT) on an SOI wafer for improving the dynamic latch-up characteristics is presented together with its numerical simulations and experimental results. The modified LIGBT structure has a p/sup +/-emitter layer between the collector and gate regions. The current at which the latch-up occurs during the turn-off transient under an inductive load is estimated in comparison with that of the conventional LIGBT. The dynamic latch-up current at room temperature and 125/spl deg/C for the modified LIGBT were 350 A/cm/sup 2/ and 290 A/cm/sup 2/, respectively. These results indicate the improvement of about 3.5 times at room temperature and about 5.5 times at 125/spl deg/C compared with those for the conventional LIGBT. This remarkable improvement in the dynamic latch-up performance is accomplished at the expense of an increase of 0.8 V in the forward voltage drop.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Static and dynamic latchup in the LIGBT

An insightful study of static and dynamic latchup in the LIGBT, based on extensive two-dimensional numerical device simulations, is described. The insight is then used as a basis for developing a physical SPICE LIGBT model, which is useful for device simulation and design (e.g. for latchup immunity) as well as for power integrated circuit simulation. The basic mechanisms underlying latchup in the LIGBT are identified for various excitations. The significance of the effective p-i-n diode that materializes via the conductivity modulation in the regenerative process is stressed in the simulations, as is the importance of non-quasi-static bipolar transistor behavior, heretofore unrecognized. the SPICE model is supported by measurements of test devices and by the numerical device simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-voltage device modeling for SPICE simulation of HVIC's

A novel methodology for flexible SPICE implementation of physical models for high-voltage power devices, accounting for their unique characteristics, is presented and demonstrated. The implementation is achieved without modifying the simulator code by utilizing user-defined controlled sources that reference a subroutine that defines the system of model equations. The simultaneous solution of the equations, which describe the integrated charges in the device and the quasistatic terminal currents in the terms of the terminal voltages, is effected by the SPICE2 nodal analysis. The methodology is exemplified by modeling the insulated-gate transistor (IGT). SPICE simulations of DC and transient characteristics of IGT switching circuits are discussed and shown to be representative of measurements. The flexibility of the modeling methodology for high-voltage integrated-circuit (HVIC) CAD is demonstrated by simulating effects of both static and dynamic latch-up in the merged bipolar/MOS structure of the IGT. >