Dual Metal Gate Research Articles

Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications

The concept of dual metal and double gate in Vertical TFET is presented to show the improvement of DC as well as analog/RF device performance standards due to enhanced gate modulation is presented in this work. This study includes the analysis of capacitances present in the device and various figures of merit (FOMs) such as transconductance (gm), cut-off frequency (fT), gain bandwidth product (GBP), transit time (τ) and transconductance frequency product (TFP) that is crucial in understanding the behavior of device for RF applications. Further from analog design point of view, it is intuitive that estimation of linearity is essential for accessing the scope of application of device. So, linearity and reliability is computed concerning higher order transconductance and VIP3, IIP3, IMD3 and 1-dB compression point of the device. The proposed TFET follows the ITRS roadmap for low standby power switch performance.

A novel design approach of charge plasma tunnel FET for radio frequency applications

In this paper, the impact of extra electron source (EES) and dual metal gate engineering on conventional charge plasma TFET (CP-TFET) have been done for improving DC and analog/RF parameters. CP-TFET structure is upgraded to double source CP-TFET (DS-CP-TFET) by placing an EES below the source/channel junction for enhancing the device performance in terms of driving current and RF figures of merit (FOMs). But, in spite of these pros, the approach is having cons of higher leakage current similar to MOSFET and negative conductance (inherent nature of TFET). Both the issues have been resolved in the double source dual gate CP-TFET (DS-DG-CP-TFET) by gate workfunction engineering and drain underlapping respectively. Additionally, for getting the optimum performance of DS-DG-CP-TFET, the device sensitivity has been investigated in terms of position of EES, length of drain electrode and workfunction of gate electrode 1 (GE1).

Interface trap-dependent linearity assessment in single and dual metal gate junctionless accumulation mode (surrounding gate) nanowire MOSFET

This paper examines the reliability issue of single metal gate (SMG) and dual metal gate (DMG) junctionless accumulation mode surrounding gate (JAM-SG) MOSFET. The impact of trap charges has also been considered along with the variation of different temperature range (200–400 K). In addition, the analog/RF performance of SMG-JAM-SG and DMG-JAM-SG MOSFET evaluated in terms of the fundamental figure of merits such as ON-state current (ION), OFF-state current (IOFF), ION/IOFF, transconductance (gm), cutoff frequency (fT), current gain, transducer power gain, VIP2, VIP3, IIP3, IMD3 and higher order transconductance parameters gm1, gm2 and gm3. An extensive comparative analysis in terms of overall performance degradation is accomplished between DMG-JAM-SG and SMG-JAM-SG MOSFET using numerical simulation tool (ATLAS 3-D). The temperature sensitivity of device has also been explained with the effect of trap charges. The results reveal that DMG-JAM-SG MOSFET has better immunity contrary to impact of interface trap charges and exhibit high linearity performance, as compared to SMG-JAM-SG MOSFET and DMG-JAM-SG MOSFET is appropriate for highly efficient RFICs and wireless device applications.

Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs

In this paper, we present a rigorous numerical simulation study on temperature sensitivity for tunnel field effect transistor (TFET). The presented temperature sensitivity analysis is studied on different digital, analog and RF figure of merits for conventional TFETs. In addition, sensitivities of the conventional TFETs are compared with proposed vertical tunneling-based TFET (V-DMGTFET) and detailed discussion is presented for the same. In comparative study, we observed that proposed V-DMGTFET is less sensitive to temperature variations compared to the conventional TFETs. This indicates that proposed V-DMGVTFET is more reliable to use in low power application at high temperatures compared to the conventional TFET.

Design structure of tunnel FET by combining thermionic emission with tunneling phenomenon

This study proposes a novel electrically doped tunnel field effect transistor (ED-TFET), which combines thermionic emission and band to band tunnelling by using an additional metal source (MS) of appropriate work function (WF; 3.9 eV) by forming an ohmic junction between metal and silicon. The ohmic junction is created below the channel region near the source channel junction by depositing of appropriate workfunction metal (lower than silicon) which injects extra electrons through over the barrier along with band to band tunneling (BTBT) in the channel of the device. Therefore, a drastic improvement in the ON state current is observed which is numerically about 107 times greater than conventional ED-TFET. Furthermore, the radiofrequency figures of merit such cut-off frequency, gain band width product, and maximum oscillating frequency are enhanced by ~10 6 , 20 and 1000 times, respectively, however, intrinsic gain and transconductance generation factor have nearly 66.66 and 14.28% improvement compared to conventional ED-TFET. Furthermore, the concepts of drain underlapping and dual metal gate have been used to checkout OFF-state current and negative conductance as a final proposal. In addition, this study has also investigated the performance variations in the proposed structure due to the WF change of CG2, length of L D1 and position of MS.

Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket

The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed Pi-NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the Pi-NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio ( $I_{\text{ON}}/I_{\text{OFF}}$ ) of 108. Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (Pi-NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of 108. Moreover, the proposed Pi-NT JLFET and Pi-NT JAMFET exhibit an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of ~ 108 and 106, respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The Pi-NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the Pi-NT transistor. The DMG-Pi-NT transistors exhibit an enhanced $I_{\text{ON}}/I_{\text{OFF}}$ ratio ~ 1011 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.

Design, Simulation and Performance Analysis of JLTFET Biosensor for High Sensitivity

In this paper, the symmetrical design of a double gate dielectric modulated junctionless tunnel field-effect transistor (DG-DM-JLTFET)-based structure is proposed and investigated and for the first time to inspect label-free recognition of biological molecules like uricase, protein, biotin, aminopropyl-triethoxysilane, etc. The point when biological molecules get immobilized in nanocavity area, the variation in the drain current, subthreshold slope, and ION/IOFF ratio has been used as the detecting parameters to recognize the sensitivity of the DG-DM-JLTFET for biomolecule recognition by using TCAD simulation. A cavity is designed by etching a layer from the substrate, at the side of the gate electrode. A dual metal gate structure is framed by utilizing two unique metal entryway anodes to decrease short channel effects of DG-DM-JLTFET. An examination is exhibited to show the effect of fill-in factor of biological molecules on drain current of DG-DM-JLTFET device. The existence of biological molecules in a small region inside the nanocavity area above the tunneling junction results in the variation of the electrical properties of the device. This brings about high sensitivity in terms of drain current, subthreshold slope, and ION/IOFF ratio. The proposed device structure gives perceptible outcomes for both (neutral and charged) types of biological molecules.

Impact of gate material engineering on ED‐TFET for improving DC/analogue‐RF/linearity performances

To avoid the fabrication complexity and cost of nanoscale devices, a dual metal gate (DMG) in polarity controlled electrically doped tunnel field-effect transistor (ED-TFET) has been introduced first time for DC, analogue/radio frequency (RF) and linearity performance improvement. The formation of n+ drain and p+ source regions are done by applying polarity biases of PG-1 as 1.2 V and PG-2 as −1.2 V, respectively, over the silicon body in DMG-ED-TFET. Different analogue/RF and linearity performance metrics of DMG-ED-TFET are evaluated using ATLAS device simulator and compared with that of ED-TFET. The figure of merits (FOMs) studied in this work for DMG-ED-TFET are in terms of transconductance, gate-to-drain capacitance, gain bandwidth product, cut-off frequency and linearity parameters such as third-order transconductance coefficient ( g m 3 ), VIP3, IIP3 and IMD3. From the simulations, it is found that DMG-ED-TFET achieves significant improvement in these FOMs as compared to ED-TFET due to introduction of dual metal at gate electrode (gate workfunction engineering). The work has also optimised the proposed device to attain optimum analogue/RF and linearity performance.

Key technologies for dual high-k and dual metal gate integration**Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA010601).

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al–O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1 (NH4OH:H2O2:H2O = 1 :1 : 5) and DHF-based solution for the selective removing of nMOS TaN and HfSiON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON. After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ N + - P - junction

We propose herein a new dual-gate metal---oxide---semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an $${N}^{+}$$N+ region on the source side with the rest consisting of a $${P}^{-}$$P- region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an $${N}^{+}$$N+ region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, $${I}_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.

Dry Etching of Metal Inserted Poly-Si Stack for Dual High-k and Dual Metal Gate Integration

Dry etching of AlN or TaN barrier layer/Mo stack (pMOS) and TaN (nMOS) in metal inserted poly-Si stacks structure for dual high-k and dual metal gate integration are investigated in detail. Firstly, in order to get a vertical profile, smooth etched surface and low Si loss, the optimal BCl3/O2/Ar plasma is developed for the etching of AlN/Mo stack. After that, both the optimal BCl3/Cl2/O2/Ar and BCl3/SF6/O2/Ar plasma are developed for the etching of TaN and TaN/Mo stack. Then, the TaN/Mo stack is chosen as the final pMOS structure since nMOS TaN metal gate will get a tapered profile under the optimal etching condition of AlN/Mo. Moreover, optimized BCl3/SF6/O2/Ar plasma is adopted for the etching of TaN and TaN/Mo stack simultaneously with both a vertical profile and a higher selectivity to the underlying layer. Finally, good electrical characteristics of CMOS device, obtained by utilizing the new developed technology, further prove that it is a practicable technology for the dual high-k and dual metal gate integration.

A Novel Gate-Normal Tunneling Field-Effect Transistor With Dual-Metal Gate

In this combined experiment and simulation study we investigate a SiGe/Si based gatenormal tunneling field-effect transistor (TFET) with a pillar shaped contact to the tunneling junction which brings forth two significant advantages. The first, is improved electrostatics at the boundary of the tunneling junction which helps to diminish the influence of adverse tunneling paths, and thus, substantially sharpens the device turn on. The second, is a simplified fabrication of a dual-metal gate using a selfaligned process. We demonstrate the feasibility of the process and show the positive effect of a dual-metal gate in experiment. Overall the paper provides general guidelines for the improvement of the subthreshold swing in gate-normal TFETs which are not restrained to the material system.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The ION/IOFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

Novel design to improve band to band tunneling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET

In this paper a cylindrical Dual Metal (DM) Dielectric Engineered (DE) Gate All Around (GAA) MOSFET has been proposed to resolve a big issue of Gate Inducted Drain leakage (GIDL) current in cylindrical Gate All Around (GAA) MOSFET to enhance the device reliability. Dual Metal Dielectric Engineered Gate All Around (DMDEGAA) MOSFET has been compared with both cylindrical Dual Metal Gate All Around (DMGAA) MOSFET and cylindrical Gate All Around (GAA) MOSFET. DMDEGAA MOSFET has larger tunneling distance than other two devices which further reduces Band To Band Tunneling (BTBT). It reduces GIDL current over other devices directing immunity from the leakages along with higher Ion/Ioff ratio showing larger applicability for digital applications. DMDEGAA MOSFET shows Subthreshold Slope (SS) close to 60 mV/decade and has higher transconductance (gm), higher Transconductance Generation Factor (TGF), higher early voltage (VEA), lower channel resistance (Rch), higher Current Gain (CG) and higher Maximum Transducer Power Gain (MTPG) for improved analog performance. DMDEGAA MOSFET also poses higher Cut Off Frequency (fT), higher Frequency Transconductance Product (FTP) and lower Total Gate Capacitance (Cgg) showing its efficacy for high speed and high frequency applications.

Ambipolarity reduction in DMG asymmetric vacuum dielectric Schottky Barrier GAA MOSFET to improve hot carrier reliability

An explicit surface potential and subthreshold current model for novel Dual Metal Gate (DMG) Asymmetric Vacuum (AV) as gate dielectric Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with the incorporation of localized charges (Nf) is developed to provide excellent immunity against threshold voltage (Vth) degradation due to hot carriers. Hot carrier induced Localized Charges (LC) either positive or negative leads to degrade the threshold of the device. The major advantage of the proposed DMG-AV-SB-CGAA MOSFET is that it mitigates the ambipolar behavior thus offering very good on current to off current ratio; and also reduces the electron temperature which leads to less hot carrier generation thus lesser degradation in Vth and improved Hot Carrier reliability.The surface potential is determined for three different regions by solving 1-D Poisson’s and 2-D Laplace equation through separation of variable method to facilitate an optimal model for calculating the subthreshold drain current from Si-SiO2 interface boundary. The developed model results are in good agreement with that of ATLAS-TCAD simulation.

Comment on “Optimization of a Pocketed Dual-Metal-Gate TFET by Means of TCAD Simulations Accounting for Quantization-Induced Bandgap Widening”

In this comment, we assess the validity of the simulation approach implemented by Beneventi et al. to account for the effects of subband discretization of conduction and valence bands in pocketed dual-metal-gate (DMG) tunnel field-effect transistors (TFETs). To do so, the authors develop a technique compatible with TCAD simulations that allows them to optimize the so far proposed semiclassical DMG-TFET configuration in terms of performance. However, we herein demonstrate analytically that their proposed technique results in increased band-to-band tunneling (BTBT) distances that notably deviate from the actual ones. This discrepancy is expected to entail a significant impact on the current levels of the device given the exponential dependence of BTBT processes on the thickness of the forbidden barrier.

Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, $$I_{\mathrm{on}} /I_{\mathrm{off}}$$Ion/Ioff ratio, transconductance, unity-gain frequency ($$f_{\mathrm{T}}$$fT), maximum oscillation frequency ($$f_{\mathrm{max}}$$fmax) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.

Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation

A novel device configuration is presented for doping-less charge plasma tunnel FET (TFET) for suppression of ambipolar nature with improved high-frequency figures of merit. For this, the drain electrode, which is used to induce n+ drain region, is separated into two sections of high and low work functions. The work function of the drain electrode section near to channel is considered relatively higher than other part for restricting the tunneling of holes at drain/channel interface for negative gate bias. This concept creates asymmetrical charge carrier concentration in the drain region, which increases the tunneling width at the drain/channel interface. Therefore, the proposed device offers better performance in terms of ambipolar current, parasitic capacitance, and RF parameters. In this regard, a comparative study of the proposed device is performed with conventional and dual-metal gate doping-less TFETs. Furthermore, the optimization of the length and higher work function of the drain electrode near to channel is discussed in detail for the proposed device. Apart from above-mentioned advantages, the doping-less nature of the proposed device provides fabrication simplicity and immunity against random dopant fluctuations in comparison with the physically doped TFET.