Abstract
The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed Pi-NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the Pi-NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio ( $I_{\text{ON}}/I_{\text{OFF}}$ ) of 108. Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (Pi-NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of 108. Moreover, the proposed Pi-NT JLFET and Pi-NT JAMFET exhibit an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of ~ 108 and 106, respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The Pi-NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the Pi-NT transistor. The DMG-Pi-NT transistors exhibit an enhanced $I_{\text{ON}}/I_{\text{OFF}}$ ratio ~ 1011 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.
Highlights
The enhanced performance of today’s state-of-the-art computational devices inherently depends on the miniaturized transistor technology
Based on calibrated 3-D simulations, we demonstrate that the proposed Pi-NT transistor architecture leads to a diminished lateral band-to-band tunneling (L-band-to-band tunneling (BTBT)) induced parasitic bipolar junction transistor (BJT) action resulting in the decrement of the OFF-state current by around 2 orders of magnitude in NT JLFETs and 3 orders of magnitude in NT junctionless accumulation mode FET (JAMFET) for a gate length of 20 nm
Based on the calibrated 3-D simulation results, we demonstrate that the Pi-NT JLFET and Pi-NT JAMFET architectures exhibit a drastically reduced OFF-state current which is attributed to the mitigated L-BTBT and a higher source-channel barrier height
Summary
The enhanced performance of today’s state-of-the-art computational devices inherently depends on the miniaturized transistor technology. The OFF-state current is considerably raised due to an enhanced L-BTBT induced parasitic BJT action, degrading their ION/IOFF This hinders the scaling and usage of NT JLFETs for low power applications irrespective of their efficient electrostatic gate control. The Pi-NT transistors exhibit suppressed L-BTBT and an enhanced immunity against the short channel effects owing to the reduction of coupling of the electric field lines of the drain with the source/channel region resulting in the reduced threshold voltage roll off at the scaled gate lengths. This leads to a reduced sensitivity of Pi-NT transistors towards gate length modulation, unlike their conventional counterpart. We show that the performance of the Pi-NT transistors can be enhanced further by incorporating the dual-material gate (DMG) engineering of appropriate work functions
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