Dual Material Gate Research Articles

Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET

FinFETs are popular and forefront runner in integrated circuits (ICs) technology due to exceptional scalability and suppressed short channel effects (SCEs). The bottom spacer (BP) concept is adopted in FinFET to achieve ameliorated short-channel, reduced self heating issues and to solve width quantization effect. The dual-material-gate (DMG) concept provides novel features like threshold voltage roll-up, transconductance enhancement and suppression of SCEs by work function engineering. Further, the ground-plane (GP) concept is also introduced to minimize the interaction between source and drain region which results in suppressed drain induced barrier lowering (DIBL). This paper investigates the systematic analysis of novel DMBSGP FinFET. The electrical performance parameters are extracted for different bottom spacer height (BSH) and workfunction differences (∆W). The analog/RF figure of merits (FOMs) such as transconductance (gm), output conductance (gd), transconductance generation factor (gm/ID), early voltage (VEA), intrinsic gain (AV), cut-off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are examined for different BSH of DMBSGP FinFET using 3-D ATLAS device simulator.

Analytical modelling and performance analysis of gate‐ and channel‐engineered trapezoidal trigate MOSFET

Here, the authors propose an analytical model to evaluate the performance of an advanced trigate MOSFET structure called trapezoidal trigate MOSFET on silicon-on-nothing (TTMSON). The model is based on the solution of Poisson's partial differential equation in three dimensions. The expression for potential distribution has been used to model other device parameters like electric field distribution, quantum inversion charge, and threshold voltage. The TTMSON device immunity to various short channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and sub-threshold swing, has been examined. A detailed analysis of the gate and channel engineering techniques like dual material gate, graded channel, and dual material gate with graded channel has also been carried out to choose the best device structural configuration for enhancing the device performance and mitigating SCEs in nano-regime. In addition, the effect of inclination angle on different performance parameters has been considered. The proposed analytical model of TTMSON has been verified by comparing the model results with the simulation results using the numerical device simulator ATLAS.

A nanoscale silicon on insulator transistor with superior performance using dual material gate and retrograde/halo doping in source/drain sides

This paper introduces two novel structures for silicon on insulator (SOI) metal-oxide-semiconductor field effect transistor (SOI-MOSFET) with nanoscale dimension and superior electrical performance. One structure only incorporates retrograde halo dopants (RHD) in the source side and uniform halo dopants in the drain side. The other device comprises dual material (DM) in the gate contact along with RHD in the source side and uniform halo dopants in the drain side (DM-RHD). Incorporation of retrograde dopants in the source side and uniform doping in the drain side of RHD and DM-RHD lead to improvements in the leakage current, sub-threshold slope and short channel effects. Hot carrier injection to the gate, channel length modulation and drain-induced barrier lowering are significantly improved with respect to the conventional SOI-MOSFET. The auxiliary gate, along with the main gate in the DM-RHD structure, improves off-current control in the channel compared with RHD and C–SOI counterparts. Because the proposed devices show these positive features, they can be utilized to satisfy International Technology Roadmap for Semiconductors requirements for next generation devices.

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

Analytical Modeling and Simulation of Nanoscale Fully Depleted Dual Metal Gate SOI MOSFET

The demand and development of scaled semiconductors devices for upcoming challenges in VLSI technology is unending. CMOS technology plays a very important role in fulfilling this criterion. The conventional MOSFET exhibits short channel effects (SCE) and performance degradation when scaled down in the nanometer regime. In order to meet the required enhanced performance and to further increase the device density new materials and new device structures have been developed. This paper analyses the performance characteristics of one of such improved device structure i.e Fully Depleted Silicon over Insulator (FDSOI) which also incorporate the gate having two metals of different work function specifically called Dual Material Gate (DMG) SOI MOSFET. The analytical modeling for this device structure has also been carried out. The simulation characteristics match closely with analytical results and as the surface potential profile of the device has step function in ensures that this device effectively reduces the SCE.

Analytical current Model for Dual Material Double Gate Junctionless Transistor

A Transistor model with bulk current is proposed in this article for long channel dual material double gate junction less transistor. The influence of different device parameters such as body thickness, channel length, oxide thickness, and the doping density on bulk current is investigated. The proposed model is validated and compared with simulated data using Cogenda TCAD. The model is designed by Poison’s equation and depletion approximation. Current driving capability of MOSFET is improved by dual material gate compare to single material gate.

Analytical current Model for Dual Material Double Gate Junctionless Transistor

A Transistor model with bulk current is proposed in this article for long channel dual material double gate junction less transistor. The influence of different device parameters such as body thickness, channel length, oxide thickness, and the doping density on bulk current is investigated. The proposed model is validated and compared with simulated data using Cogenda TCAD. The model is designed by Poison’s equation and depletion approximation. Current driving capability of MOSFET is improved by dual material gate compare to single material gate.

An In0.53Ga0.47As/In0.52Al0.48As Heterojunction Dopingless Tunnel FET With a Heterogate Dielectric for High Performance

In this paper, an In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As heterojunction dopingless tunnel field-effect transistor (HDL-TFET) with an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> heterogate dielectric is proposed, where the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -pocket with variable electron concentration can be formed by adjusting the length of source-side channel (LSC) based on the charge plasma concept, instead of employing conventional ion implantation or dual-material gate techniques. It aims to improve the device performance and simplify the device fabrication. At the drain bias of 0.3 V, numerical simulations show that the on-state current (ION) of the HDL-TFET with LSC = 4 nm can approach ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> A/μm that is far higher than that of the Si-DL-TFET (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/μm), and the average subthreshold swing (SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> ) can approach 36.6 mV/decade that is significantly lower than that of the Si-DL-TFET (89.2 mV/decade). It is also found that the drain-induced barrier lowering (DIBL) effect and the ambipolar current can be effectively suppressed in the HDL-TFET because of an existence of heterojunction. Under the condition of low gate and drain biases, the HDL-TFET exhibits peak values of the cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and the maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) approaching 13 and 4.73 GHz, respectively, while the Si-DL-TFET yields those of 8.05 and 2.26 GHz, respectively, under relatively higher biases. It indicates that the HDL-TFET is a promising device for low-power consumption radio frequency applications.

An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO2

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO₂

Comparison study of Dual Material Gate Silicon on Insulator junctionless Transistor and with Junction Transistor for Analog Performance

Comparison study of Dual Material Gate Silicon on Insulator junctionless Transistor and with Junction Transistor for Analog Performance

Subthreshold analytical model for dual-material double gate ferroelectric field effect transistor (DMGFeFET)

In this work, an analytical model for dual-material double gate ferroelectric field effect transistor (DMGFeFET) has been developed to investigate the impact of dual-material gate (DMG) and ferroelectric insulator on electrostatic integrity of the device. Landau–Khalatnikov equation along with Poisson’s equation has been used to obtain various parameters such as potential profile distribution, threshold voltage roll-off, drain induced barrier lowering, subthreshold slope etc. The results obtained have been comprehensively compared with equivalent dual-material double gate FET (DMGFET) and it has been demonstrated that DMGFeFET leads to significant improvement in gate controllability as well as substantial reduction in DIBL values. Furthermore, the proposed device exhibits reduction in subthreshold current by 3 orders as compared to conventional DMGFET, thereby implying reduced static power dissipation and efficient device operation. The results obtained using developed model have been validated by numerical simulation results obtained by ATLAS Silvaco tool.

Quasi-analytical model-based performance analysis of dual material gate stack strained GAA FinFET

ABSTRACT The evolution of traditional field effect transistor from planar to three-dimensional (3-D) device structure has led to higher package density and high current drive. However, due to continuous scaling, these non-planar devices (FinFET) have been found to suffer from performance degrading short channel effects (SCEs). In this work, a modified field effect device called dual material gate-all-around FinFET with High-K Gate-Oxide stack and strained channel is presented along with its quasi 3-D analytical model to evaluate the SCE immunity. This surface potential-based model includes gate work-function difference, characteristic gate length and equivalent oxide thickness. The channel potential is derived using quasi-3-D scaling equation where the characteristic length is derived using equivalent number of gates model. With the simple expression of potential distribution, threshold voltage and subthreshold swing have been obtained using minimum central potential. The device immunity to SCEs such as drain-induced barrier lowering, hot carriers and subthreshold degradation has also been examined for various structural and material modifications. The proposed analytical model has been verified using the 3-D numerical device simulator ATLAS.

An Analytical Modeling and Simulation of Surrounding Gate TFET with an Impact of Dual Material Gate and Stacked Oxide for Low Power Applications

In this paper, an analytical model for modified Surrounding Gate Tunnel FET with gate stack engineering and different gate metals has been developed. Further, considering the scaling advantageous of Gate stack engineering and high degree performance of dual material engineering, the both has been integrated into a novel structure known as Surrounding Gate (SG) Tunnel FET with stacked oxide SiO2/high-k and dual material (DM) has been proposed. The two dimensional (2D) potential at the surface and electric field mathematical models for the DMSG TFET are developed by solving 2D Poisson's equation with matching device boundary conditions. Based on the Kane's formula, mathematical expression for the band-to-band (BTB) tunneling generation rate is derived and then used to calculate the drain current. The impact on the proposed device performance due to the variation of different device parameters has also been studied. It has been found from the presented results that the ON current of the DMSG TFET with stack is 10-6A, OFF current is 10-13A and ON/OFF ratio is 107. The mathematical results have been verified using the simulated results obtained from TCAD, a 3-D device simulator from ATLAS.

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

ABSTRACTIn this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.

Quantum modeling of threshold voltage in Ge dual material gate (DMG) FinFET

An analytical model for threshold voltage of Ge dual material gate (DMG) FinFET by self consistently solving 3D Poisson’s and 2D Schrödinger’s equation is developed. The model includes the quantum effects as well. The potential distribution in the channel region is developed by solving 3D Poisson’s equation. The expression for wave function and quantized energy levels are derived by solving 2D Schrödinger’s equation. The model for inversion charge is derived by using the expression of quantized energy levels. The threshold voltage model is derived by equating inversion charge with the threshold charge estimated from TCAD simulator. The proposed models are validated with a numerical simulator for a wide range of geometrical parameter and drain bias values.

A 2-D Modeling of Fe doped Dual Material Gate AlGaN/AlN/GaN High Electron Mobility Transistors for High Frequency Applications

The prototype of Fe doped Dual Material Gate AlGaN/AlN/GaN High Electron Mobility Transistors(HEMTs) developed by a Finite Difference Method(FDM) is addressed in this paper. The equations are illustrated in a way that the dual material gate disintegrates into two distinct single material gates by discreting one 2-D equation into two isolated equations. The boundary conditions conclude in the clubbed model of two 1D equations. The work functions of two metal gates, their length difference and applied drain voltage, the proposed model estimates the Channel potential, Electric field, Threshold voltage and Drain current. A momentous increase of the drain current is witnessed when the δ-doping is integrated in the AlN layer. These features are also validated by TCAD simulations.

Investigation of Localized Charges and Temperature Effect on Device Performance of Ferroelectric Dual Material Gate All Around TFETs

Investigation of Localized Charges and Temperature Effect on Device Performance of Ferroelectric Dual Material Gate All Around TFETs

Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket

The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed Pi-NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the Pi-NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio ( $I_{\text{ON}}/I_{\text{OFF}}$ ) of 108. Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (Pi-NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of 108. Moreover, the proposed Pi-NT JLFET and Pi-NT JAMFET exhibit an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of ~ 108 and 106, respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The Pi-NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the Pi-NT transistor. The DMG-Pi-NT transistors exhibit an enhanced $I_{\text{ON}}/I_{\text{OFF}}$ ratio ~ 1011 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.

A New Effective-Conducting-Path-Driven Subthreshold Behavior Model for Junctionless Dual-Material Omega-Gate Nano-MOSFETs

In this paper, a generalized analytical subthreshold behavior model for junctionless omega-gate (JLΩG) MOSFETs combining dual-material gate (DMG) is built. Through the effective conducting path effects (ECPEs), we propose a new concept of off-center ratio (δ) dominating the effective scaling length to derive our model based on the effective conducting central potential (Φ eff,C ), obtained by quasi-3D potential method. It provides a more accurate expression of scaling equation for JLΩGFETs and leads to an improved subthreshold behavior prediction. Accounting for these renewed potential and current models, we utilize dual materials to achieve better immunity to short channel effects. The proposed modeling can be extensively applied to other multiple-gate (MG) nano-transistors as well.