Dual Material Gate Research Articles

Analytical modelling for surface potential of dual material gate overlapped-on-drain TFET(DM-DMG-TFET) for label-free biosensing application

This article presented the first-ever 2D analytical model for the surface potential of dual material gate overlapped-on-drain TFET (DMG-TFET) device for label-free biosensor application using dielectric modulation technique. The use of two different metal work functions for the gate (ϕM1<ϕM2) impacts the device’s surface potential to increase tunneling width at the secondary tunneling junction to enhance the device sensitivity compared to single material gate device. This model takes into account the effect of changing the dielectric constant value, location, and percentage of fill factor of the target biomolecules on the surface potential of the device. The parabolic approximation of surface potential is used for solving the 2D-Poisson’s equation by applying suitable boundary conditions. The analytical surface potential results are verified with the simulation result using the SILVACO Atlas tool.

Qualitative Analysis of Dual Material Gate (SiO2/HfO2) Underlapped on Drain Side TFET (DMGUD-TFET) Using Work Function Engineering

Qualitative Analysis of Dual Material Gate (SiO2/HfO2) Underlapped on Drain Side TFET (DMGUD-TFET) Using Work Function Engineering

Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors

In this paper, a dopingless DRAM based on work function engineered Tunnel field effect transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF current ratio of drain current, thereby improving the sense margin and retention time. Drain electrode is made up of dual metal, so as to suppress ambipolar current. The analysis of dual material gate dual drain electrode DRAM (DMG DDE DRAM) and triple material gate dual drain electrode DRAM (TMG DDE DRAM) is done in terms of retention time and sense margin. The performance parameters with different device dimensions and bias conditions are analyzed. It is observed that the proposed DRAMs work well even when the dimensions are scaled down. In addition, the proposed DRAMs have comparable performance with the conventional DRAMs and provide better performance when compared with other dopingless DRAM. Retention times of 430 ms and 370 ms, sense margins of 130 nA and 101 nA are achieved with TMG DDE DRAM and DMG DDE DRAM respectively.

Analytical Exploration and Simulation of Dual-Material Gate Macaroni Channel MOSFET biosensor using dielectric-modulation technique

The paper presents extensive analytical modeling and simulation of a novel Dual-Material Gate Macaroni-Channel MOSFET to act as a biosensor for detection of neutral as well as charged biomolecules using dielectric modulation approach. Dielectric modulation in a MOSFET device is the alteration in the dielectric constant in the gate dielectric region of the device. Presence of biomolecules (in a nanogap etched under the gate of the projected device) having different dielectric constants impact the gate capacitance that in turn affects the device features such as potential, threshold voltage, drain current which undergo considerable shift in presence of biomolecules. Detailed Sensitivity analysis based on threshold voltage shift for different types of biomolecule allows suitable detection of biomolecule type. Suitable selection of device outer radius allows significant suppression of some major Short channel effects such as threshold voltage reduction, reduced subthreshold swing enabling superior device performance. Finally, comparative sensitivity analysis of the proposed device with its full channel Cylindrical Gate-all-around counterpart having same channel thickness exhibits better sensitivity capability of the proposed device for both neutral and charged biomolecule. Analytical results are substantiated using Atlas simulation outputs.

Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node

Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node

Novel Attributes and Analog Performance Analysis of Dual Material Gate FINFET Based High Sensitive Biosensors

Novel Attributes and Analog Performance Analysis of Dual Material Gate FINFET Based High Sensitive Biosensors

Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

Effect of Step Gate Work Function on InGaAs p-TFET for Low Power Switching Applications.

In this study, we theoretically investigated the effect of step gate work function on the InGaAs p-TFET device, which is formed by dual material gate (DMG). We analyzed the performance parameters of the device for low power digital and analog applications based on the gate work function difference (∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate electrodes. In particular, the work function of the drain (ϕD) side gate electrodes was varied with respect to the high work function of the source side gate electrode (Pt, ϕS = 5.65 eV) to produce the step gate work function. It was found that the device performance varies with the variation of gate work function difference (∆ϕS-D) due to a change in the electric field distribution, which also changes the carrier (hole) distribution of the device. We achieved low subthreshold slope (SS) and off-state current (Ioff) of 30.89 mV/dec and 0.39 pA/µm, respectively, as well as low power dissipation, when the gate work function difference (∆ϕS-D = 1.02 eV) was high. Therefore, the device can be a potential candidate for the future low power digital applications. On the other hand, high transconductance (gm), high cut-off frequency (fT), and low output conductance (gd) of the device at low gate work function difference (∆ϕS-D = 0.61 eV) make it a viable candidate for the future low power analog applications.

Dual gate material (Au and Pt) based double-gate MOSFET for high-speed devices

Aluminium Gallium Arsenide (AlGaAs) is a semiconductor material used in the latest design of double heterostructure laser diodes. This semiconductor is mostly available in the arbitrary alloy form between Gallium Arsenide and Aluminium Arsenide. It is derived from the Tri-MethylGallium (TMG/TMGa), and Arsine (AsH3), both the chemicals are pyrophoric and toxic. The resistance is less between source and drain contacts in the case of AlGaAs so that it has been proposed as a material to grow contacts on Indium Phosphide (InP) layer. The AlGaAs uses an ion implantation model for a design purpose which lowers the thermal power while the operation of the device. The parasitic capacitance has to be taken care of while designing a device using this material since the capacitance affects much in the AlGaAs based devices. The average velocity of the electrons has been observed to be increased by 14.63 % in the Au-gate (gate-1) and Pt-gate (gate-2) material-based Double-Gate (DG) MOSFET compared to the Silicon-based DG MOSFET. This paves the way for higher electron mobility, in turn, it can be used in highfrequency device manufacturing. The proposed material can be used in high-speed hybrid applications such as HEMTs and radiofrequency devices for long-haul communication.

Modelling and Analysis of Dual Material Gate Charge Plasma Based Vertical t-shaped TFET

Modelling and Analysis of Dual Material Gate Charge Plasma Based Vertical t-shaped TFET

A dual gate material tunnel field effect transistor model incorporating two‐dimensional Poisson and Schrodinger wave equations

AbstractThis paper presents an accurate analytical model of surface potential and drain current for a long channel dual material gate (DMG) tunneling field‐effect transistor (TFET) with the addition of nonlinear inversion charge developed at the channel/drain interface region, ambipolar characteristic, and quantum confinement. The model includes the effect of dual metal gate work function as it controls the threshold voltage without considering a fully depleted undoped channel region. The current model includes the effect of charge accumulation at the interface of two gates and an appropriate mathematical expression of nonlinear inversion charge developed at the interface of two gates has been derived from the two‐dimensional (2D) Schrodinger wave equation incorporating quantum confinement. The model is effective to capture transfer characteristics at Sub 10 nm body thickness. A high ION/IOFF ratio and less than 27 mV/decade subthreshold swing are achieved at 2 nm body thickness which is desirable for low power VLSI application. The proposed model has been compared and calculated by Sentaurus TCAD with fair accuracy and a good resemblance, including ambipolar characteristics at sub 10 nm body thickness has been achieved.

Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor

Aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) has shown great potential and superiority over other devices in high power and high speed-based systems [1-4]. Recently, a novel AlGaN/GaN HEMT structure named triple material gate (TMG) HEMT has been proposed in [5] in which the gate contact is composed of three metals with different work functions. TMG HEMT ensures high carrier velocity and better suppression of short channel effects. In this work, a two-dimensional electro-thermal model has been developed to investigate the joule heating effect in TMG AlGaN/GaN HEMT using the software COMSOL [6]. The current continuity and heat transport equations are solved self-consistently to obtain the temperature distribution profile in various layers of the device. Thermal efficiency of TMG HEMT is compared with dual material gate and single material gate HEMT. It has been found that, besides providing better current carrying capability, TMG HEMT shows optimum thermal performance. Moreover, the variation of peak temperature in the channel with drain and gate voltages is analyzed to study the bias voltage dependence of the device temperature rise. Effects of several device parameters like total channel length, spontaneous and piezoelectric polarization induced charges and ratio of lengths of control and screen gates, on the thermal performance have also been explored. Simulations are carried out for the device lying on different substrate materials (Sapphire, GaN, Si and SiC) with varying thermal conductivity to demonstrate their performance in heat removal capacity. This simulation model can serve as a very useful tool to comprehend the thermal behavior of the device for high power and high frequency applications.

Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor

A two-dimensional electro-thermal model has been developed to investigate the Joule heating effect in triple material gate (TMG) aluminum gallium nitride (AlGaN) / gallium nitride (GaN) high electron mobility transistor (HEMT) using the software COMSOL. The current continuity and heat transport equations are solved self-consistently to obtain the temperature distribution profile in various layers of the device. By comparing with dual material gate and single material gate HEMTs, it has been found that, besides providing better current carrying capability, TMG HEMT shows optimum thermal performance. Effects of several device parameters like total channel length, spontaneous and piezoelectric polarization induced charges and ratio of lengths of control and screen gates, on the thermal efficiency have been explored. Bias voltage and underlying substrate material dependence of the device operation have also been investigated.

Investigation of Gate Material Engineering in Junctionless Transistor for Digital and Analog Applications

In this paper, we propose dual material gate with dual-k dielectric gate oxide double gate junctionless transistor ‘DMG-DK-JLT’ for significant enhancement of performance. We showed, using 2D simulation that the proposed DMG-DK-JLT exhibit: 1) suppressed gate induced drain leakage due to band to band tunneling in OFF state (VDS = 1 V, VGS = 0 V) by 5 orders. 2) Impressively high ION/IOFF ratio of ~108. 3) For VGS=VDS = 1 V, DMG-DK-JLT performs better over conventional double gate JLT on various digital and analog performance metrics such as transconductance (Gm, 64% improvement), early voltage (VEA, 107% improvement), intrinsic gain (GmRO, 294% improvement), unity gain cutoff frequency (fT, 48% improvement), output resistance (Ro, 139% improvement), and transconductance-to-drain current ratio (Gm/ID, 218% improvement at VGS = 0.2 V, VDS = 1 V). We also compared its performance on above metrics with other gate material engineered Junctionless transistors. Moreover, we also show these values are further improved several orders by adding high-k gate sidewall spacer to our proposed DMG-DK-JLT.

Analytical modeling analysis and simulation study of dual material gate underlap dopingless TFET

An analytical model of dual material single gate doping-less Tunnel FET (DM-GU-TFET) with gate underlap regions has been proposed. The potential of gate underlap area with channel area has been examined using modeling and the results are validated using TCAD simulation at boundary conditions. The proposed structure has been divided into ten distinct sections (counting source/drain depleted sections) to get potential models while settling the 1-Dimensional and 2-Dimensional Poisson equations (PE) condition in the respective sections. To settle the PE's at different limit conditions, explanatory estimate strategy is proposed and tested. The effect of geometric morphology, for instance under-lap length, has been analyzed, which is dependent on electrical attributes of DM-GU-TFET. The parabolic approximation technique is used to settle the PE's at various interface conditions. The effect of structural variations viz. gate underlap length and tunneling length is scrutinized using electrical characteristics of DM-GU-TFET. The resultant characteristics of proposed dopingless TFET represent a noteworthy improvement in surface potentials with variation in length of spacer region, underlap section and tunneling region.

Study of a Gate-Engineered Vertical TFET with GaSb/GaAs0.5Sb0.5 Heterojunction.

It is well known that the vertical tunnel field effect transistor (TFET) is easier to fabricate than the conventional lateral TFETs in technology. Meanwhile, a lightly doped pocket under the source region can improve the subthreshold performance of the vertical TFETs. This paper demonstrates a dual material gate heterogeneous dielectric vertical TFET (DMG-HD-VTFET) with a lightly doped source-pocket. The proposed structure adopts a GaSb/GaAs0.5Sb0.5 heterojunction at the source and pocket to improve the band-to-band tunneling (BTBT) rate; at the same time, the gate electrode is divided into two parts, namely a tunnel gate (M1) and control gate (M2) with work functions ΦM1 and ΦM2, where ΦM1 > ΦM2. In addition, further performance enhancement in the proposed device is realized by a heterogeneous dielectric corresponding to a dual material gate. Simulation results indicate that DMG-HD-VTFET and HD-VTFET possess superior metrics in terms of DC (Direct Current) and RF (Radio Frequency) performance as compared with conventional VTFET. As a result, the ON-state current of 2.92 × 10−4 A/μm, transconductance of 6.46 × 10−4 S/μm, and average subthreshold swing (SSave) of 18.1 mV/Dec at low drain voltage can be obtained. At the same time, DMG-HD-VTFET could achieve a maximum fT of 459 GHz at 0.72 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 35 GHz at Vgs = 0.6 V, respectively. So, the proposed structure will have a great potential to boost the device performance of traditional vertical TFETs.

Performance evaluation of junctionless double surrounding gate In0.53Ga0.47As nanotube MOSFET using dual material gate engineering

In this paper, the authors present the studies made on drain current (ID) for 5 nm gate length Dual Material (DM) Double Surrounding Gate (DSG) inversion mode (IM) and junctionless (JL) In0.53Ga0.47As nanotube (NT) MOSFET and Silvaco ATLAS 3D TCAD based simulation results are reported. In these studies, the authors have made use of the Non-Equilibrium Green’s Function (NEGF) approach and the self-consistent solution of Poisson’s equation with Schrodinger’s equation. In the case of inversion mode nanotube MOSFET, the channel region is lightly doped. The effect of Dual Material Gate Engineering for In0.53Ga0.47As Nano Tube channel radius 1.5 nm with gate oxide (Al2O3) thickness (0.8 nm) on ID, has also been studied. Further, a comparison of results has been done between IM DM DSG and JL DM DSG NT MOSFET. In the case of JL MOSFET, doping concentrations are optimized for two approaches (i) to get the same ION current as IM device and (ii) to get the same threshold voltage (VTH) as IM device. This results in 10 and 102 times smaller IOFF in matching ION and VTH optimized devices respectively as compared to IM device. It was found that DM Gate Engineering reduces drain induced barrier lowering (DIBL) in IM and JL devices. JL device is found to have much smaller DIBL ~ 21.10 mV/V, almost an ideal SS ~ 60 mV/dec, and a higher ION/IOFF ratio ~ 2.85 × 108 as compared to the results available for CGAA devices in the literature.

Digital Performance Assessment of the Dual-Material Gate GaAs/InAs/Ge Junctionless TFET

FIn this article, a device called GaAs/InAs/Ge junctionless tunnel field-effect transistor (JL-TFET) is proposed and investigated by a numerical simulator. This device utilizes an InAs pocket at the source side and its digital performance parameters such as subthreshold slope (SS) and ON-state current to OFF-state current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio have been improved in comparison with GaAs/Ge JL-TFET. Simulation results show that the electron tunneling mechanism is based on intraband tunneling and interband tunneling in GaAs/InAs/Ge JL-TFET, while the electron tunneling mechanism is interband tunneling in regular JL-TFET. To further reduce SS, we have proposed for the first time GaAs/InAs/Ge JL-TFET structure with a fixed gate (f-gate), the so-called dual-material gate (DMG) GaAs/InAs/Ge JL-TFET. The f-gate induces a local dip in the conduction band edge leading to more abrupt band bending at the vicinity of the InAs/GaAs interface. Simulation results show that DMG GaAs/InAs/Ge JL-TFET is turned on at lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> compared to GaAs/InAs/Ge JL-TFET, causing a SS is improved. A brief examination of the proposed device has been done on the impacts of both the variations of the f-gate work-function (φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> ) and the f-gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f-gate</sub> ). The DMG GaAs/InAs/Ge JL-TFET with a channel length of 20 nm, φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> = 3.7 eV, and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f-gate</sub> = 5 nm showed the average SS of SS = 2.1 mV/dec, and ON-state current of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 0.51 mA/μm. The SS and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of the DMG GaAs/InAs/Ge device are improved by 150% and 76%, respectively, compared to the GaAs/Ge JL-TFET device with similar dimensions. The DMG GaAs/InAs/Ge JL-TFET device proposed in this article can be a reasonable candidate for digital applications.

Analysis on effect of lateral straggle on analog, high frequency and DC parameters in Ge‐source DMDG TFET

The diffusion of doping concentration in source/drain regions through ion implantation technique extents to the channel, which decreases the inversion portion of channel and results in variation of device behavior. In this paper, by merging the advantages of Ge-source TFET and dual material gate (DMG) TFET, a new device named as Ge-source dual material double gate (DMDG) TFET is proposed. We have investigated DC parameters like drain current vs gate bias, drain current vs drain bias, subthreshold swing (SS), and current ratio (ION/IOFF) by changing the lateral straggle parameter (σ) from 0 to 5 nm through TCAD device simulator in proposed TFET. The RF/analog behavior like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd), total gate capacitance (Cgg), cut-off frequency (fc), transconductance generation factor (TGF), transconductance frequency product (TFP), gain frequency product (GFP), and gain transconductance frequency product (GTFP) are reported for different σ values in proposed TFET. It is found that both DC and RF/analog figure of merits are a function of σ. It is perceived that ION as well as RF/analog characteristics are improved, whereas, short channel parameter degrades with increase in σ. Finally, the effect of σ on noise performance and s-parameters are highlighted in proposed device.

Band gap and gate metal engineering of novel hetero-material InAs/GaAs-based JLTFET for improved wireless applications

This paper investigates the reliability of a dual metal gate-hetero-material junctionless tunnel FET (DMG-HJLTFET), by using a novel combination of III–V compound semiconducting materials, $$\mathrm{InAs}$$ (lower bandgap) in the source region and $$\mathrm{GaAs}$$ (higher bandgap) in the channel and drain regions. We applied bandgap engineering and dual material gate engineering to improve the linearity metrics and distortion parameters by optimizing an appropriate lower work function tunnel gate toward the source and higher work function supplementary gate toward the drain and compared all the results with SMG (single metal gate)-HJLTFET and Si-JLTFET. The DMG-HJLTFET showed marked improvements in terms of ION, ION/IOFF, SS, $${g}_{\mathrm{m}}$$ , $${g}_{\mathrm{m}3}$$ , VIP2, VIP3, and 1-dB compression point. The input power, IIP3 of DMG-HJLTFET, is 158% greater than SMG-HJLTFET and is 154.7% greater than Si-JLTFET. The distortion power, IMD3 of DMG-HJLTFET, is 171.8% and 20.5% lower than SMG-HJLTFET and Si-JLTFET, respectively, thereby making it suitable for low-power distortion-free wireless communication systems.