Digital Performance Assessment of the Dual-Material Gate GaAs/InAs/Ge Junctionless TFET

Abstract

FIn this article, a device called GaAs/InAs/Ge junctionless tunnel field-effect transistor (JL-TFET) is proposed and investigated by a numerical simulator. This device utilizes an InAs pocket at the source side and its digital performance parameters such as subthreshold slope (SS) and ON-state current to OFF-state current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio have been improved in comparison with GaAs/Ge JL-TFET. Simulation results show that the electron tunneling mechanism is based on intraband tunneling and interband tunneling in GaAs/InAs/Ge JL-TFET, while the electron tunneling mechanism is interband tunneling in regular JL-TFET. To further reduce SS, we have proposed for the first time GaAs/InAs/Ge JL-TFET structure with a fixed gate (f-gate), the so-called dual-material gate (DMG) GaAs/InAs/Ge JL-TFET. The f-gate induces a local dip in the conduction band edge leading to more abrupt band bending at the vicinity of the InAs/GaAs interface. Simulation results show that DMG GaAs/InAs/Ge JL-TFET is turned on at lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> compared to GaAs/InAs/Ge JL-TFET, causing a SS is improved. A brief examination of the proposed device has been done on the impacts of both the variations of the f-gate work-function (φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> ) and the f-gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f-gate</sub> ). The DMG GaAs/InAs/Ge JL-TFET with a channel length of 20 nm, φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> = 3.7 eV, and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f-gate</sub> = 5 nm showed the average SS of SS = 2.1 mV/dec, and ON-state current of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 0.51 mA/μm. The SS and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of the DMG GaAs/InAs/Ge device are improved by 150% and 76%, respectively, compared to the GaAs/Ge JL-TFET device with similar dimensions. The DMG GaAs/InAs/Ge JL-TFET device proposed in this article can be a reasonable candidate for digital applications.