Dual Material Gate Research Articles

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics

Herein, we report an AlGaN channel metal insulator semiconductor high electron mobility transistor (MISHEMT) in dual material gate (DMG) architecture with two different dielectrics as gate insulator for enhancing the DC performance of the device. The use of a high-k dielectric material as gate insulator below gate metal 1 and a low-k dielectric below gate metal 2 results in significant threshold voltage variation along the channel. This contributes to improved average carrier velocity which in turn results in better current drive. The proposed device exhibits a peak current of 162 mA/mm at zero gate bias, whereas, the DMG and single material gate (SMG) AlGaN channel HEMTs offer currents of 137 mA/mm and 125 mA/mm respectively. The peak transconductances are about 24.66 mS/mm, 23.68 mS/mm and 22.71 mS/mm respectively for the proposed device, DMG and SMG HEMTs. The proposed device reduces the OFF current by an order of 106 compared to that of DMG HEMT.

Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

In this work, the trap sensitivity of single material gate (SMG) and dual material gate (DMG) nano ribbon FETs (NRFETs) are reported using TCAD Sentaurus Device simulator. The trap sensitivity is extracted for Gaussian trap distribution of both acceptor and donor type traps. We have reported the trap sensitivity for the variation in trap concentration, energy peak position, work function of metal gate, and temperature for both the NRFETs. It is realized that trap sensitivity is greater and lesser than 100% for acceptor type trap in SMG and DMG NRFETs, respectively, whereas, such sensitivity is 147% and 123% for donor type trap concentration, respectively. Temperature also shows a significant variation in trap sensitivity for both the NRFETs. The increase in work function leads to the reduction in trap sensitivity for both NRFETs in existence of acceptor and donor trap charges. The maximum sensitivity in trap are 400% and 275% for SMG and DMG NRFETs, respectively, in presence of donor trap concentration. Moreover, the trap sensitivity is very insignificant at high gate bias for donor type trap concentration with wide variation in parameters.

A Novel high-voltage DMG Fe-doped AlGaN/AlN/GaN HEMTs with sheet charge density model

In this work, two-dimensional electron gas of the dual material gate Fe doped AlGaN/AlN/GaN High Electron Mobility Transistors (HEMTs) device, sheet charge density model is demonstrated. The model is constructed by considering the electron charge in the barrier layer and the quasi triangular quantum well. This sheet charge density is calculated by Fermi-Dirac statistics by the formation of various sub energy bands and it is valid for all bias voltages. Higher carrier densities are produced and the introduction of the Fe-doped AlN layer reduces the electrons penetration to pass through the AlGaN barrier layer. The model's transcoductance variation is basically constant over an extensive variety of gate source voltages, thereby rendering it perfect regarding high-performance amplifications. The developed analytical model is demonstrated and the simulation results are validated with TCAD simulation. A good agreement is achieved with both analytical and simulation results for all of the voltages employed and device geometries.

Phosphorene nanoribbon field effect transistor with a dual material gate

In this paper, we present a dual-material gate phosphorene nanoribbon field-effect transistor (DMG-PNRFET) that combines the advantages of a PNRFET with a DMG configuration. In this structure, the difference in the work function creates an extra barrier for band-to-band tunneling from the valence band (VB) to the conduction band (CB) inside the channel leading to lower off-currents. An illustration for transmission coefficients with relevant band diagrams is included to demonstrate energy-resolved current spectrum and tunneling emissions within the transport window for both on and off-states. Results also show that DMG-PNRFET possesses a higher ION/IOFF ratio, delay, and power delay product (PDP) compared to a conventional PNRFET. Hence, the DMG-PNRFET is better suited for digital applications. Our simulations rely on combining the density functional-based tight binding method with the non-equilibrium Green’s function.

Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

This article presents a detailed investigation of the High-K dielectric horizontal stack spacer (HSS) dual material gate junction-less FinFET device for analog and RF application using the gate oxide stack (GOS) approach. At first, the impact of the horizontal stack spacer (HSS) with different high-K spacer materials are investigated by placing different dielectric material like HfO2, SiO2, Si3N4, and TiO2 on the horizontal spacer. The simulation results of the device indicate that the High-K dielectric HSS makes the device high stability toward the leakage current and static power dissipation at the sub-nano scale regime. The DC characteristics of the device are also investigated alongside the AC/RF characteristics. The proposed device predominantly improves performance in terms of parameters like subthreshold swing, Ion/Ioff, and DIBL. The proposed device shows a high ON current of 8.56 × 10−5 A μm−1, which is about 15% higher than the existing literature, and the device also makes a notable impact on the leakage current by restricting it to 9.635 × 10−12 A/μm. The simulation of the device is carried out with optimization of the doping to investigate and improve the device’s performance. The device shows an excellent improvement in performance which is highly suitable for future-ready device applications.

Design and Simulation of Dielectrically Modulated Dual Material Gate-Stack Double-Gate FinFET Biosensor

This study developed and evaluated a dual-material gate stack double-gate FinFET-based biosensor (DM-GS-DG FinFET). The device was dielectrically modulated and investigated for molecules, such as streptavidin, gluten, zein, hen egg-white lysozyme, and acetylene tetrabromide, based on current, threshold voltage, subthreshold swing, and switching sensitivity. The influence of charged and neutral biomolecules within the nanocavity on the electric, analog, and radiofrequency parameters was recorded. This study was conducted relative to different dielectric κ-values of 12 in terms of the percentage sensitivity improvement (SI%). The results reveal that the percentage of sensitivity ION improves effectively, especially for low κ-values, compared with other sensitivity measures. All the sensitivity evaluations indicated that DM-GS-DG-FinFET combined with biomolecules is a viable option for biosensing purposes.

Enabling of CMOS Circuit using Dual Material Gate Germanium Pocket Induced FDSOI MOSFET

This research presents a comparison of the electrical performance of a double-side induced germanium-pocket (IGP) FD-SOI MOSFET and a dual material gate IGPFDSOI (DIGPFDSOI). The electrical performance is reviewed by comparing the device parameters like drain current, band diagram, lateral electric field, surface potential, and work function of the gate material. The proposed structure exhibits excellent characteristics compared to the IGPFDSOI MOSFET. The proposed structure has a greater Ion/Ioff ratio, a lower subthreshold slope, reduced capacitance, and an elevated cut-off frequency. The implementation of a dual metal gate is considered a superior method in comparison to FD-SOI technology because it effectively reduces the negative effects of scaling. A study is being done to analyze the differences in the work functions of metal gates to evaluate the effectiveness of the proposed construction. The comparison evaluation shows that the suggested design can be used for both digital and analog tasks because it has a higher switching frequency and a better cut-off frequency. Apart from this, the proposed structure can also be implemented without making substantial changes to the conventional FD-SOI MOSFET fabrication process flow. Here, we are using n-type and p-type DIGPFDSOI MOSFETs to make a CMOS converter circuit. Sentaurus TCAD is used to simulate and analyze the performance of the proposed structure.

The Effect of a Dual Oxide - Dual Gate Material and a Sensitivity Analysis on the Performance of a Junctionless Tunnel FET

The Effect of a Dual Oxide - Dual Gate Material and a Sensitivity Analysis on the Performance of a Junctionless Tunnel FET

Analytical modeling of drain current for DG-Graphene Nanoribbon Vertical Tunnel FET

The semi-classical current transport model is used in this study to examine the drain current model for Double-Gate (DG) Dual-Material-Gate (DMG) Graphene-Nanoribbon (GNR) Vertical TFETs. It takes into account the contact potential (VGS, VDG), the impact of the oxide thickness (tOX), and the carrier mobility (μ). The device’s channel length is 50 nm, and the energy bandgap is 0.26 eV when the GNR ribbon width is 10 nm. The bandgap varies with the GNR ribbon width. The data from the simulation of TCAD tools are compared to an analytical result of the drain current. The current transport model shows good agreement. It is clear that a GNR with a 5 nm width can switch ON and OFF at 0.5 V drain voltage, which shows low power bias operation. The suggested GNR-TFET is capable of producing an average subthreshold current of 16 mV/Dec, 1.74 × 10−4 A/μm on-state current, and 1.66 × 10−18 A/μm off-state current. The exceptional performance is made possible by the narrow bandgap, high mobility, and two-dimensional (2-D) nature of GNR.

Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects

This work investigates the impact of the self-heating effect (SHE) on SOI Dual-Material Gate (DMG) FinFETs with channel engineering including gate underlapped and overlapped structures. Both these structures are compared with conventional DMG FinFET to detect the possible effects of SHE on DC characteristics and thermal parameters. The drop rates of ON current (ION), Off-current (IOFF), Maximum transconductance (gm,max), ION/IOFF ratio, and Drain-induced barrier lowering (DIBL) are calculated to get the precise results. For extensive thermal reliability analysis, the two main distinguishing parameters lattice temperature and thermal resistance are also calculated and their dependency with gate/drain bias and operating temperature are also explored. Comparison between thin and thick BOX devices aimed at distinguishing possible effects of SHE on BOX thickness variation. The result shows that the SHE greatly improves ION/IOFF ratio by 220.8% in gate underlap structure due to large reduction in leakage current. Although lattice temperature is higher in gate overlap structure but thermal resistance decreases by 53.6 % due to its high ON current. Using high-k dielectric BOX materials, small improvement in device SHE characteristics is also accomplished.

Design and Analyze the Effect of Hetero Material and Dielectric on TFET with Dual Work Function Engineering

Background: As the size of the field effect transistors is reduced down to nanometers, the performance of the devices is affected by various short-channel effects. To overcome these effects, various novel devices are used. Tunnel Field Effect Transistors (TFET) are novel devices in which the drain current needs to be improved. Gate engineering and III-V compound materials are proposed to improve the ON current and reduce the leakage current along with its ambipolar behaviour. Methods: The proposed device structure is designed with a heterojunction hetero dielectric dual material gate Tunnel Field Effect Transistor incorporating various combinations of III-V compound materials such as AlGaAsSb/InGaAs, InGaAs/Ge, InGaAs/InP and SiGe/Si. As in III-V composite materials like AlGaAsSb/InGaAs, the narrower bandgap at the source channel interface helps to improve the electric field across the junction. At the same time, the wider bandgap at the channel drain junction leads to unidirectional current flow, resulting in ambipolar reduction. 2D TCAD simulation is used to obtain the electrical parameters for Hetero junction TFETs and the comparison analysis of different Hetero device structures. Results: The device's electrical parameters, such as energy band diagram, current density, electric field, drain current, gate capacitance and transconductance, have been simulated and analyzed. Besides, the dual material used in the gate, such as Metal1 (M1) and Metal2 (M2), along with HfO2/SiO2 stacked dielectric, helps improve the gate controllability over the channel and the leakage current reduction. Conclusion: An ION=10-1A/μm, IOFF = 10-12A/μm at drive voltage 0.5V is obtained for InGaAs/InP layer at the source channel hetero junction TFET, and ION=10-2A/μm, IOFF =10-14A/μm at drive voltage 0.5V is obtained for SiGe/Si layer at the source channel hetero junction TFET. Therefore, the InGaAs/InP and SiGe/Si layer TFET are more suitable for ultra-low power integrated circuits.

A ballistic model for subthreshold current and threshold voltage of the dual-material-gate nanosheet MOSFET

— A ballistic model for subthreshold current of the dual-material-gate (DMG) nanosheet (NS) MOSFET is developed based on the Landauer approach, three-dimensional scaling equation, and the continuity of subthreshold current at the interface between the control gate and screen gate in the channel, The work function difference between the screen gate and control gate can be converted into the new interface-quasi-fermi-potential (IQFP) at the junction between different gate regions. Through the IQFP, the ballistic subthreshold current for DMG NS MOSFET is successfully developed. With the determined subthreshold current, the ballistic threshold voltage can also be achieved by the constant current method. Under the low and high drain voltage corresponding to their IQFPs, the subthreshold behavior is mainly governed by the contact potential and thermal voltage, respectively. Furthermore, Ohm's law regarding ballistic resistance for the DMG NS MOSFET can still be valid in the subthreshold conduction.

Oppositely-Doped Core-Shell Junctionless Nanowire FET: Design and Investigation

Junctionless Nanowire Field Effect Transistor (JL-NWFET) has garnered significant attention in recent years owing to its simplified fabrication process, achieved through uniform doping across the device. However, JL-NWFET suffers from certain drawbacks, including low drive current, insufficient volume depletion, and lateral band-to-band tunneling. To address these issues, this paper proposes Improved JL-NWFET with an oppositely doped core–shell structure along with a Dual Material gate (DMG) and high-k spacer. Furthermore, Improved JL-NWFET is optimized for parameters such as core thickness, gate oxide material, spacer material, and spacer length. The performance of Improved JL-NWFET is also evaluated in comparison with other structural variants of JL-NWFET. Notably, Improved JL-NWFET showcases an enhancement of 23.1% and 20% in ON-state current (I ON ) and transconductance (g m ), respectively when compared to the conventional JL-NWFET. Furthermore, the Subthreshold Slope (SS) experiences an 88% improvement in the Improved JL-NWFET as opposed to the JL-NWFET. Additionally, the OFF-state leakage current (I OFF ) undergoes a fivefold reduction, leading to a sixfold increase in the I ON /I OFF ratio compared to the JL-NWFET. Among all the variants of JL-NWFET devices analyzed in this paper, Improved JL-NWFET stands out with its exceptional performance characteristics.

Surface Potential Analysis of Dual Material Gate Silicon-Based Ferroelectric TFET for Biosensing Application

By means of a dielectric modulation method, this research offers the first ever 2D analytical model for the surface potential of a dual material gate Ferroelectric-TFET (DMG-Fe-TFET) device used in an enzyme-free biosensor. Compared to a device with a single material gate, the sensitivity of a device with a gate made of two distinct metals (M1-M2) is improved by an increase in tunnelling width at the secondary tunnelling junction. This model accounts for the change in surface potential caused by varying the value, position, and fill factor of the target biomolecules. Several distinct device architectures are used to enhance the efficiency of the envisaged Fe-TFET in the nanoscale range. We also investigated how the dimensions of the Nano cavity and other parts of the device affect its sensitivity. In addition, simulation findings using the SILVACO Atlas platform are used to confirm the results obtained when testing the DMG Fe-TFET’s sensitivity in comparison to other recently manufactured FETs.

Optimized Nano Scaled Drain and Gate Engineered Schottky Barrier MOSFET with improved Ambipolarity and RF Characteristics

In this work, a novel structure of Schottky Barrier MOSFET (SB-MOSFET) has been presented. The proposed device consists of dual material gate and electrostatically doped drain, and the device is...

Comparison study of RF/analog and linearity performance of dual material gate graphene source vertical TFET (DMG-GR-VTFET) and single material gate GR-VTFET

This paper investigates the comparative feature of Graphene Source Single Material Gate Vertical Tunnel FET (SMG-GR-VTFET) and Graphene Source Double Material Gate VTFET (DMG-GR-VTFET) on DC, analog/RF and linearity applications using Sentaurus TCAD simulator. The results show that both devices outperforms in DC characteristics, including ambipolar current, subthreshold swing (SS), ION/IOFF ratio etc The study focuses on important figures of merit (FOMs) such as transconductance (gm), output conductance (gd), cut-off frequency (ft), second-order transconductance (gm2), third-order transconductance (gm3), VIP2, and VIP3, which are all improved due to high mobility of graphene leads to improved band-to-band tunneling. The observed ION is 5.2 × 10−4 (1.1 × 10−3 A/μm), IOFF is 1.439 × 10−13 (2.28 × 10−16A/μm) and ION/IOFF ratio of 3.613 × 109 (4.824 × 1012) for SMG-GR-VTFET (DMG-GR-VTFET), respectively. It is seen that maximum gm is 2.96 × 10−3 (2.59 × 10−3 S μm−1) and cut-off frequency (ft) values of 1.1 × 1011 (1.85 × 1011 Hz) for SMG-GR-VTFET (DMG-GR-VTFET), respectively. Regarding the Linearity parameter VIP2 value is 2.71 V (0.99 V), respectively, for SMG-GR-VTFET (DMG-GR-VTFET). These results suggest that Graphene Source Vertical Tunnel FET is an excellent choice for analog and high-frequency applications.

Examining the design characteristics of a dual-material gate all-around tunnel FET for use in biosensing applications

Abstract An inventive analytical model for a dual material gate-all-around tunnel FET with possible applications in biosensors is described in this study. The semiconductor device considered in this study has a gate-all-around configuration built with two distinct materials. Short-channel effects are avoided with the help of the surrounding gate to achieve flexibility. A breakthrough dual-material design with a nanocavity has been developed to render it viable for biosensing applications. To figure out Poisson’s equation and to derive its surface potential, the Finite Differentiation Method is used in this work. The electric field, subthreshold swing, drain current, and threshold voltage of the suggested structure are then determined using this potential. Furthermore, the device’s biosensor sensitivity is examined and the results are verified by two-dimensional TCAD simulations.

Analysis on the impact of interface Trap distributions on SOI DMG FinFETs: Overlap/underlap configurations

This paper investigates the significance of interface trap charges (ITCs) distribution by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator on dual-material gate (DMG) FinFETs in gate Overlap and Underlap configurations in terms of DC and analog/RF parameters. Different charge density profiles like Uniform and Gaussian distribution of traps are considered at different energy levels for both donor and acceptor ITCs to evaluate the devices reliability. It is observed that the donor traps mainly affects the OFF-state current (IOFF) by insignificantly, while, acceptor traps mainly impacts ON state current significantly. The impact of Acceptor ITCs on various parameters such as transfer characteristics, electron density, conduction band energy, transconductance (gm), total gate capacitance (Cgg), device efficiency (gm/ID), and cut-off frequency (fT), for DMG FinFETs have been comprehensively analysed at trap concentration N0=1×1013 and compared with no traps among the three devices. An acceptor trap charges with Gaussian distribution has larger impact on devices performance. It degrades the ON state-current by 36.09 %, 25.72 %, and 41.9 % for conventional, Overlap, and Underlap configurations, respectively. It is evident from the results DMG underlap configuration is more vulnerable to ITCs, attributed to its larger interface charge region due to the increase in effective channel length while, the overlap configuration is more immune towards ITCs as, lesser electrons get trapped. Thus, the overlap configuration is the most reliable among underlap and conventional configurations.

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10−17 A μm−1) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.