Dual-gate Structure Research Articles

Trap-Induced Data-Retention-Time Degradation of DRAM and Improvement Using Dual Work-Function Metal Gate

Data retention time distribution of the dynamic random-access memory cell transistor of the 20-nm technology generation has been investigated using the physics-based statistical simulation. Traps cause high leakage current of the leaky cells; however, we found that the reduction of trap is not effective in improving the refresh cycle. Therefore, an effective method is needed to overcome the retention time degradation due to the traps. This study shows that the data retention time of the tail cells can be increased more than 50% by adopting the dual work function metal gate structure.

Feasibility of a Dual-Gate Graphene Transistor to Test Various Gate Dielectrics for Two-Dimensional Device Application

Graphene transistors with a dual-gate structure have been fabricated to study the effects of a functional dielectric substrate. From graphene’s conductance modulation by using dual-gate voltage control in which a polymethyl methacrylate (PMMA) layer is employed as a top-gate dielectric, we propose that the interaction between the graphene and the functional material working as a back-gate dielectric substrate can be understood. We evaluated two graphene devices, one having the standard structure of Si/SiO2/graphene/PMMA/top-gate and the other employing periodically poled lithium niobate (PPLN) with the structure of PPLN/graphene/PMMA/top-gate. The feasibility of this approach is discussed in terms of the effect of the alternating polarization domains on graphene’s charge transport.

Analysis of a Schottky Barrier MOSFET for Synaptic Device Using Hot Carrier Injection

In this paper, we analyze the hot carrier injection (HCI) in an asymmetric dual-gate structure with a metallic source/drain. We propose a program/erase scheme where HCI occurs on the source side of the body. Owing to the large resistance of the Schottky barrier used, a large electric field is formed around the Schottky barrier. Therefore, impact ionization occurs as the gate voltage is increased and hot carriers are injected into the source side, which is less influenced by the drain voltage. We also analyze the program and erase efficiency by adjusting the Schottky barrier height or by using dopant segregation technique. We expect a small amount of current to flow and great efficiency of the program/erase operations to use as a synaptic device.

Characteristics of Dual‐Gate Graphene Thermoelectric Devices Based on Voltage Regulation

A dual-gate graphene thermoelectric device structure is proposed. Under the control of back-gate and top-gate voltage, the type and degree of carrier transport in graphene channels can be changed, where the absorption and release of heat are controlled at the contact between graphene and metal electrodes. More details can be found in article number 1901466 by Xiumin Gao and co-workers.

Deep Gate Field Penetration Au:ZrO2 Metal–Insulator Tunneling Transistor

A new class of metal–insulator tunneling transistor (MITT) devices is proposed and investigated. The planar dual-gate structure allows for complete gate field penetration of the transistor channel to modulate tunneling current across the channel. For a 5-nm channel length, with contact geometries that reflect the reality of fabricating at such a scale, we show that a 10% decrease in the effective electron tunneling length results in a $5.5\times $ increase in current up to $4.4{\times }10^{-6} mA/\mu {}m$ . The device demonstrates an ON-/ OFF-current ratio that is $2.5\times $ greater than that of a complementary metal–oxide–semiconductor (CMOS)-style MITT with a 5-nm channel length. Without the use of a second gate insulator, the source-to-drain current density is more than 104 times greater than the source-to-gate leakage current density, indicating the efficacy of the presented realistic MITT implementation.

Dual-gate crystalline oxide-nanowire field-effect transistors utilizing ion-gel gate dielectric

Dual-gate structure field-effect transistors (DG FETs) can provide various advantages such as high output current, enhanced mobility, and tunability of threshold voltage (VTH) by adversely controlling the two channels formed at both top and bottom gate dielectric interfaces. Here, we present high-mobility DG structure FETs using crystalline Ga-doped In2O3 (IGO) nanowires (NWs) as channel and high-k ion-gel as a top gate dielectric layer. To enhance the electrical properties of IGO NW FETs such as field-effect mobility, on/off ratio, VTH, and subthreshold slope, optimization of electrospinning, Ga doping in In2O3 NWs, and thermal annealing was carried out. The optimized IGO NW FETs with a single SiO2 gate dielectric exhibited field-effect mobility of ~6.0 cm2/(V·s), on/off ratio of >107, subthreshold slope of 0.73 V/decade, and VTH of ~0 V. Also, the IGO NW FETs showed excellent operation stabilities under positive-gate-bias and negative-bias-illumination stress conditions. Furthermore, by using a high-k ion-gel film as the second gate dielectric layer, DG IGO NW FETs with field-effect mobility up to ~35.1 cm2/(V·s) were realized which is comparably higher than those of single-gated IGO NW FETs (6.0–6.5 cm2/(V·s)).

Surface potential-based analytical model for InGaZnO thin-film transistors with independent dual-gates**Project supported by the National Key Research and Development Program of China (Grant No. 2017YFA0204600) and the Fundamental Research Funds for the Central Universities of Central South University, China (Grant No. 2019zzts424).

An analytical drain current model on the basis of the surface potential is proposed for indium–gallium zinc oxide (InGaZnO) thin-film transistors (TFTs) with an independent dual-gate (IDG) structure. For a unified expression of carriers’ distribution for the sub-threshold region and the conduction region, the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation, and to derive the potential distribution of the active layer. In addition, the regional integration approach is used to develop a compact analytical current–voltage model. Although only two fitting parameters are required, a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD. The proposed current–voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.

High-performance dual-gate-charge-plasma-AlGaN/GaN MIS-HEMT

This paper presents a novel structure of dual-gate-charge-plasma (DG-CP) AlGaN/GaN metal–insulator–semiconductor high electron mobility transistor (MIS-DG-CP-HEMT) with gate oxides employing Al2O3. AlN as an interfacial layer between dielectric and semiconductor. Dual-gate technique for both CP and doped HEMT is used to improve the transport characteristics in the channel. CP-HEMT is used to enhance the conductance charge density and electron concentration at the interface of AlGaN and GaN. The DG-CP-HEMT is compared with DG-doped HEMT. The dual-gate structure helps in incorporating the two different layers of 2-dimensional electron gas (2DEG) for higher current density. Results showed a better performance of DG-CP-HEMT in term of various analog and RF parameters. HEMT gives better transconductance (29 mS), Cutoff frequency (11 GHz) and ON-state-to-OFF-state current ratio (1011), ON-resistance (6 Ω-cm2) and subthreshold slope (63 mV/dec). The proposed HEMT architecture can be used for RF applications due to its exemplary characteristics.

Transparent Flexible High Mobility TFTs Based on ZnON Semiconductor With Dual Gate Structure

High mobility thin film transistors (TFTs) based on zinc oxynitride (ZnON) semiconductor were fabricated onto polyethylene-2.6-naphthalate (PEN) substrates. The application of a dual gate structure enhanced the field-effect mobility from 65.8 to 147 cm2/ $\text{V}\cdot \text{s}$ , which is generally attributed to the bulk accumulation effect. Dual gate driving also results in improved device stability with respect to bias and illumination stress. This is most likely due to the fact that the bulk channel confines the charge carriers away from the semiconductor-dielectric interfaces, where charge trapping is anticipated. The electrical performance of dual gate devices did not change significantly after 5,000 bending cycles, while the single gate transistors exhibited clear degradation.

A Compact Short-Channel Analytical Drain Current Model of Asymmetric Dual-Gate TMD FET in Subthreshold Region Including Fringing Field Effects

A compact drain current model is developed for an asymmetric, dual gate, monolayer 2 - D Transition metal dichalcogenide (TMD) field effect transistor (FET) in the subthreshold region. The work includes the effect of source to drain tunneling and gate dielectric fringing effects. The model is systematically derived for an asymmetric, dual gate structure. The model developed is also extended into a dual-gate symmetric structure. The characteristic length expression has only physical and dimensional parameters including the contribution of fringing field effects from both front and back gate dielectric. The model is validated with simulation results obtained using NEGF based nanodevice simulators and experimental data of WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> p-channel FET. Also, transfer characteristics, output characteristics, subthreshold swing and output resistance are compared with reported data in literatures. A close agreement is observed with some disparity arising because of the non-inclusion of back gate fringing effects and source to drain tunneling in their models. The proposed model captures the effects of different high-κ gate dielectric materials and its thicknesses. Impact of temperature is also studied on transfer characteristics. The model is also scalable from ultrashort channel regime to long channel regime. Finally, the model can be applicable not only for TMD materials but other 2 - D materials also.

Solving Overlapping Pattern Issues in On-Chip Learning of Bio-Inspired Neuromorphic System with Synaptic Transistors

Recently, bio-inspired neuromorphic systems have been attracting widespread interest thanks to their energy-efficiency compared to conventional von Neumann architecture computing systems. Previously, we reported a silicon synaptic transistor with an asymmetric dual-gate structure for the direct connection between synaptic devices and neuron circuits. In this study, we study a hardware-based spiking neural network for pattern recognition using a binary modified National Institute of Standards and Technology (MNIST) dataset with a device model. A total of three systems were compared with regard to learning methods, and it was confirmed that the feature extraction of each pattern is the most crucial factor to avoiding overlapping pattern issues and obtaining a high pattern classification ability.

Inhibiting the Kink Effect and Hot-Carrier Stress Degradation Using Dual-Gate Low-Temperature Poly-Si TFTs

This study examines the appearance of a kink effect phenomenon in the I $_{\mathbf {D}}$ -V $_{\mathbf {D}}$ electrical characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after high-current-induced hot-carrier stress (HCS). During HCS, electron–hole pairs were generated in the channel near the drain terminal owing to impact ionization. Next, the electrons were repelled towar the source by the drain electric field, thereby inducing the floating body effect, which lowered the source barrier. In addition, a dual-gate-structured LTPS was found to inhibit the electrical degradation caused by HCS. The COMSOL simulation indicated that in the dual-gate structure, holes at the upper and lower margins of the channel were inverted and inhibited the degradation caused by the floating body effect. Therefore, the use of dual-gate LTPS TFTs could facilitate high-current gate-on-array circuit applications in display panels.

Impact of two gate oxide with no junction metal oxide semiconductor field effect transistor- an analytical model

Abstract An analytical model based on physics is used to describe the potential distribution, horizontal electric field, and drain current of Two Gate Oxide with no junction MOSFET (TOX-NOJ-MOSFET) was investigated for cylindrical shape structure. The Poisson equation is used to derive the expression for cylindrical coordinate system which relies on parabolic approximation method. The combination of high k two gate oxide stack and junctionless transistor with Dual material Double gate structure performs a major role to diminish the short channel effects, propelled to increase the ION current (10−5A/μm) and decrease the leakage current IOFF of 10−14 A/μm to enhance ION/IOFF ratio to 109. To ensure the scalability and responsiveness of the system numerical simulations have been performed with various bias voltages and gate length ratios using Synopsys TCAD software and the results were well matched with analytical solutions.

Dual-Gated MoS2 Neuristor for Neuromorphic Computing.

The field of neuromorphic computing systems has been through enormous progress in recent years, whereas some issues are still remaining to be solved. One of the biggest challenges in neuromorphic circuit designing is the lack of a robust device with functions comparable to or even better than the metal-oxide-semiconductor field-effect transistor (MOSFET) used in traditional integrated circuits. In this work, we demonstrated a MoS2 neuristor using a dual-gate transistor structure. An ionic top gate is designed to control the migration of ions, while an electronic back gate is used to control electronic migration. By applying different driving signals, the MoS2 neuristor can be programmed as a neuron, a synapse, or an n-type MOSFET, which can be seen as a fundamental building block in the neuromorphic circuit design. The MoS2 neuristor provides viable solutions for future reconfigurable neuromorphic systems and can be a promising candidate for future neuromorphic computing.

Analysis of Hot Carrier Injection According to Gate Length.

In this paper, we analyze hot carrier injection (HCI) in an asymmetric dual gate structure with a charge storage layer. In a floating gate device, holes injected by HCI can move freely in the valence band, since the channel potential is constant. In case of charge trapping layer, however, holes are trapped only in the drain side where impact ionization occurs. Therefore, only small threshold voltage shift occurs because channel formation is enhanced only in the drain side. When the gate length is under 100 nm, trapped holes in the drain side start to control the whole channel. Thus, we expect that HCI into the charge trapping layer can be used as a non-volatile memory (NVM) mechanism in short channel devices.

Polysilicon-Based Synaptic Transistor and Array Structure for Short/Long-Term Memory.

In this paper, we proposed and fabricated a polysilicon-based four-terminal synaptic transistor. The device has an asymmetric dual-gate structure. The top gate, which uses a thin SiO₂ layer as the gate dielectric, is the input terminal of the synaptic transistor, which receives spikes from pre-synaptic neurons. Meanwhile, a nitride trapping layer was inserted between the channel and the bottom gate to serve as a non-volatile memory. The bottom gate is the node that receives the post-neuron feedback signals and adjusts the synaptic weight. With this double-gate structure, the proposed artificial synapse can perform short-/long-term memory operations. In addition to the basic unit cell characteristics, a highly integrated synapse array structure is also proposed. In our array structure, the top gate is tied in the word-line direction to accept the input signal. Drain contacts are also tied in the same direction. With regard to bit-line direction, the source terminals are tied to carry post-synaptic signals and the bottom gate line receives feedback signals from the post-synaptic neurons.

Improvement in DC and pulse characteristics of AlGaN/GaN HEMT by employing dual metal gate structure

This paper presents the fabrication and electrical characterization of dual metal gated high electron mobility transistors (DMG-HEMTs) on AlGaN/GaN/SiC hetero-structure using oblique and normal angle deposition of Nickel and Titanium respectively as gate metals. A noteworthy advance in the device characteristics has been achieved including DC and pulse drain current, transconductance, ON-resistance. The upsurge in DC drain current and transconductance is ∼8% and 11% respectively. Pulse I–V measurements have been executed to evaluate the dynamic performance of DMG-HEMTs. Pulse I–V unveils significant improvement in drain lag, gate lag and current collapse in these devices which is due to the redistribution of electric field under the gate.

Orders-of-magnitude enhancement in conductivity tuning in InGaZnO thin-film transistors via SiNx passivation and dual-gate modulation

The mobility of pristine amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) is insufficient to meet the requirement of the future ultra-high-definition displays. Reported herein is the fabrication of hydrogenated long-channel IGZO TFTs exhibiting a transconductance and an on/off ratio that are orders of magnitude superior to those of the regular devices. The gate bias stability of the treated IGZO TFTs was greatly enhanced, with the threshold voltage shifting by less than 1 V after 1 h stress. Experimentally, the hydrogenation of the active layer was achieved via the deposition of a SiNx/SiOx bilayer on top of the IGZO via plasma-enhanced chemical vapor deposition followed by post-annealing under optimized conditions. The elemental depth profiles indicated that this enhanced performance originated from the hydrogen doping of the IGZO film. Furthermore, a dual-gate structure was fabricated to alleviate the deterioration of the subthreshold properties induced by the excess hydrogen doping.

Nanoscale dual-gate InAlAs/InGaAs HEMT with improved characteristics

ABSTRACT This paper deals with the DC and Radio Frequency (RF) characteristics of InAlAs/InGaAs-based dual-gate high-electron-mobility transistor (DG-HEMT) for a 50 nm gate length. In single-gate HEMT (SG-HEMT), the gate length having less than 100 nm shows poor transconductance (g m ) which reduces the voltage gain (A v ) and maximum oscillation frequency (f max). To overcome this problem, a dual-gate structure is designed keeping the device dimensions unchanged and a numerical model is developed to study the effect of the dual gate. A comparative study of SG-HEMT and DG-HEMT is presented. For a DG-HEMT, a maximum drain current (Ids ) of 310 mA/mm at Vds = 0.1 V, a peak transconductance (g m_max) of 2294 mS/mm, a cut-off frequency (fT ) of 100 GHz and a maximum oscillation frequency (f max) of 270 GHz have been achieved. For reduced gate length, the DG-HEMT performs better due to the presence of dual gate and double heterojunction.

Improved pH Sensitivity and Reliability for Extended Gate Field-Effect Transistor Sensors Using High-k Sensing Membranes.

In this study, we fabricated extended-gate (EG) field-effect transistor (FET) pH sensors with dualgate (DG) structures, using a range of dielectric sensing membranes (SiO₂, Si₃N₄, HfO₂ and Ta₂O5) to vary their sensitivity. The fabricated EGFETs consisted of a silicon-on-insulator (SOI)-based metal-oxide semiconductor field-effect transistor (MOSFET) transducer and an EG sensor. We amplified the sensitivity of the device far beyond the Nernst limit (59 mV/pH), which is the theoretical maximum of conventional ion-selective FET (ISFET) sensing, by applying capacitive coupling. Among the evaluated dielectric sensing membranes, we obtained the highest sensitivity (478 mV/pH), low hysteresis (100.2 mV) and drift rate (24.6 mV/h) from the pH sensor with a Ta₂O5 membrane. Hence, we expect DG FET configurations using Ta₂O5 films as EG sensing membranes to be useful for high performance biosensor applications, as they satisfy the requirements for sensitivity, stability and reliability.