Trap-Induced Data-Retention-Time Degradation of DRAM and Improvement Using Dual Work-Function Metal Gate

Abstract

Data retention time distribution of the dynamic random-access memory cell transistor of the 20-nm technology generation has been investigated using the physics-based statistical simulation. Traps cause high leakage current of the leaky cells; however, we found that the reduction of trap is not effective in improving the refresh cycle. Therefore, an effective method is needed to overcome the retention time degradation due to the traps. This study shows that the data retention time of the tail cells can be increased more than 50% by adopting the dual work function metal gate structure.