DRAM Applications Research Articles

Silicides as contact material for DRAM applications

TiSi, CoSi, CoSi 2 and NiSi are used for a salicide contact metallisation in DRAM devices. The contact resistance is studied: for contacts to tungsten silicide-gates, for self-aligned n-type contacts in the memory cell array and for large borderless n-type and p-type contacts in the chip periphery. It is shown that the contact resistance on p-type contacts is reduced with CoSi by at least 40% compared to TiSi and NiSi, whereas the contact resistance of cell array-, gate- and n-type contacts is comparable for the different silicides. In order to enable a sufficient retention time the leakage current is critical. Due to the low silicon consumption NiSi contacts result in the smallest leakage. Using a Cobalt + Ti-Cap stack the Si leakage currents rise by orders of magnitude. It is shown that with a TiN-cap and a changed chemistry for the selective strip leakage currents as small as for TiSi can be achieved. The role of CoSi-thickness and the formed silicide-phase, i.e., CoSi or CoSi 2, on contact resistance and leakage current are discussed.

Highly Reliable MIS Capacitors With Plasma Nitridation and Doubled Dielectric-Constant Tantalum Pentoxide

We studied effective thinning of metal-insulator-semiconductor tantalum pentoxide capacitors experimentally for DRAM application. First, we investigated the dielectric constant of a tantalum pentoxide film deposited and crystallized on an oxidation-resistant thick silicon-nitride film. Dependence of electrically equivalent thickness on physical thickness of tantalum pentoxide revealed an increased dielectric constant of 60, whereas the films on a silicon-dioxide film had a dielectric constant of no more than 40. To apply this increased dielectric constant to DRAM capacitors, we applied novel plasma nitridation on the surface of polysilicon. The plasma-nitrided surface showed fair oxidation resistance up to 800/spl deg/C, at which a tantalum pentoxide film fully crystallizes. The temperature was 100/spl deg/C higher than that of a conventional treatment using rapid thermal nitridation (RTN). The improved oxidation resistance enabled the increased dielectric constant as well as suppression of silicon oxide between the film and polysilicon. Consequently, effective thinning by 10% was demonstrated even on rugged polysilicon without increase of leakage current. Time-dependent dielectric-breakdown measurements revealed that the tantalum pentoxide capacitors fabricated using plasma nitridation are expected to have a lifetime three orders of magnitude longer than that of those fabricated using RTN.

Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W∕WNx∕poly-Si gate MOSFET for high density DRAM applications

We have studied the effects of the gate hard mask and the gate spacer nitride film on the reliability of W∕WNx∕poly-Si gated devices. When the gate hard mask nitride film is used, severe degradation of the stress-induced leakage current (SILC) and the interface trap density (Dit) characteristics are observed in the large metal-oxide-semiconductor (MOS) capacitors. On the other hand, as the devices become smaller, the effects of the hard mask nitride film are relieved. The gate spacer stack plays a more critical role in the reliability of smaller devices. The oxide∕nitride (ON) spacered devices exhibit better reliability in terms of SILC, Dit, threshold voltage (Vth) shift, and transconductance (Gm) compared to those of the nitride∕oxide∕nitride (NON) spacered ones. These behaviors are explained by the mechanical stress of the nitride films.

Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications

High performance delay-locked loop (DLL) is key to the high data rate chip-to-chip communication, suggesting the output jitter, due to power noise, bang-bang noise, temperature-voltage drift, etc, should be properly controlled. In this paper, high speed DRAM operation can be achieved by a dual loop DLL with various novel techniques; a new counting code with hysteretic bit-transitions can remove the large DAC glitches by preventing the binary bit-transitions in the locking states. A delay buffer, which is insensitive to the power supply fluctuations, is proposed. The voltage-temperature (VT) dependencies of the feedback path and the open clock path are balanced, minimizing the VT shift of the clock. As a result, the high-speed DRAM interface with the maximized setup/hold window can be accomplished.

Characterization of barium strontium titanate thin films for tunable microwave and DRAM applications

Ba 0.5Sr 0.5TiO 3 thin films have been deposited on Pt/TiO 2/SiO 2/Si substrates by the pulsed laser deposition technique (PLD) while varying the temperature, oxygen pressure, substrate to target distance and laser energy. The structural characterization of the BST thin films was performed by X-ray diffraction (XRD) and atomic force microscopy (AFM). The electrical characteristic of the capacitors was assessed by the vector network analyzer (VNA). A tunability of 3.1:1 and loss tangent of 0.0121 were achieved at 0.4–0.8 GHz for tunable microwave applications. The effect of using strontium ruthenium oxide (SrRuO 3) as electrodes for BST has been explored for DRAM applications. The SrRuO 3 film was deposited by PLD and was used as bottom and top electrodes. The BST-based capacitors show reasonable dielectric constants and thus have been proven to be very reliable memory devices.

Silicon nanocrystal based memory devices for NVM and DRAM applications

Si nanocrystal based devices have shown potential in reducing the operating voltages used in continuous floating gate FLASH devices. We discuss the critical aspects of this technology––nanocrystal formation by CVD, nanocrystal passivation, and HCI/FN mode of operation of non-volatile memory bitcells fabricated using a 0.13 μm CMOS process technology. The superior FN erase characteristics of nanocrystal memory compared to a SONOS device are demonstrated, which enables the use of thicker tunnel oxides in nanocrystal memory devices as required to mitigate READ disturb. It is shown that nanocrystal area coverage of <25% is optimal for effective charge isolation and for 2-bit/cell applications. Finally the potential of this technology for use in a 1-transistor PMOS DRAM cell is discussed.

Etching mechanism of (Pb,Sr)TiO3 thin films for DRAM application using Cl2/Ar inductively coupled plasma

Etching mechanism of (Pb,Sr)TiO3 thin films for DRAM application using Cl2/Ar inductively coupled plasma

Etching mechanism of (Pb,Sr)TiO 3 thin films for DRAM application using Cl 2/Ar inductively coupled plasma

Etching characteristics of (Pb,Sr)TiO 3 (PST) thin films were investigated using inductively coupled chlorine-based plasma system as functions of gas mixing ratio, radio frequency power and direct current bias voltage. It was found that the increasing of Ar content in gas mixture lead to sufficient increasing of etch rate and selectivity of PST to Pt. The maximum etch rate of PST film is 56.2 nm/min and the selectivity of PST to Pt is 0.8 at Cl 2/(Cl 2+Ar) of 0.2. It was proposed that sputter etching is dominant etching mechanism while the contribution of chemical reaction is relatively low due to low volatility of etching products.

Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance

The write/erase characteristics of Germanium nanocrystal memory device are modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects. A trap model is proposed to describe the retention characteristic of the nanocrystal memory. The impact of nanocrystal size, tunnel-oxide thickness, and high-k tunnel material is studied, and the suitability of the nanocrystal memory devices for nonvolatile memory and DRAM applications is discussed. Issues related to the scaling limit of the nanocrystal memory device are investigated.

Dielectric Properties of Ba0.5Sr0.5TiO3 Thin Films from DC to Ka Band

Much of the interest in Ba0.5Sr0.5TiO3 (BST) thin films has focused on DRAM applications. For this application, the most studied characteristics have been the dielectric constant and the leakage current, both of which are usually measured either at DC or at low frequencies. A few studies have made use of impedance measurements in the 100 Hz to 100 MHz range. Unfortunately, all these measurements fall far short of current DRAM speeds, which are quickly approaching 1 GHz. Other technologies, such as digital computing and wireless communications are already well into the microwave range. The importance of microwave characterization of BST films is therefore clear. Such a characterization technique is described and results from DC to Ka band are presented.

Transient effects in PD SOI MOSFETs and potential DRAM applications

The transients in partially depleted (PD) silicon on insulator (SOI) MOSFETs produced with 0.25 and 0.13 μm technologies are studied. The exponential dependence of the switch-on transient time on the reciprocal drain voltage for both P- and N-channel devices is explained by the predominance of the impact ionisation mechanism. A pulse method to measure output I– V curves using short gate pulses has been applied to study self-heating and transient effects in 0.13 μm SOI N-MOSFETs. It is shown that under normal operating conditions the difference between DC and pulsed I– V curves of PD SOI MOSFET is attributed mainly to the floating body effect and not to self-heating. We demonstrate also that it is possible to use the body charging of PD SOI devices to store information. Based on this effect, an original 1T-DRAM cell concept is proposed (DRAM: dynamic random access memory). This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor. This concept allows the manufacture of low cost DRAMs and embedded DRAMs for 100 and sub-100 nm generations.

Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications

Threshold voltage (V/sub t/) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-/spl mu/m single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N/sub 2/ implant prior to gate oxidation is important to reduce V/sub t/ roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V/sub t/ roll-off characteristics. Finally, the impact of halo implant on V/sub t/ variation in sub-0.2-/spl mu/m buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V/sub t/ variation in sub-0.2-/spl mu/m single workfunction gate pFET.

Study Of Ta2O5 Based MOS Capacitors, With Tantalum Oxidized In O2:NH3 Ambient.

AbstractTantalum Pentaoxide, an alternative to SiO2, as a high-k dielectric for DRAM and MOS applications, faces the problem of interface mismatch at silicon. SiO2 or Si3N4 interfacial layer could help in overcoming this problem. The higher band offsets of these materials also help in the reduction of leakage currents at low electric fields. Here we study the physical and electrical characteristics of Ta, oxidized in O2:NH3 ambient, and without any other interface layer. This is done to check if N/H moves to the interface, and thus improves the electrical properties. XRD studies of the film, showed the presence of Ta2O5. Peaks corresponding to TaSi2, un-oxidized tantalum and TaN were also found in the film. But the intensity of these peaks decreased with the reduction of NH3 content. Thus a higher oxygen content could reduce the content of TaN and unoxidized tantalum. FTIR analysis however showed strong Ta=O and Si-O peaks. For the MOS capacitors, due to the presence of resistive components, the maximum capacitance was reduced, compared to that of pure Ta2O5 films. Oxide charges in the films were observed to be around 1.9E10 cm-2. But the traps in these films were found to be almost negligible as observed from the negligible hysteresis in the C-V characteristics. Films with N/H showed lesser oxide charges by an order of magnitude, as compared to pure Ta2O5 films.

Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-/spl mu/m CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield.

Study of Thickness Dependence on Electrical Properties of (Pb,La)TiO 3 Thin Films for Memory Applications

Lead-lanthanum- titanate (Pb 0.72 La 0.28 ) TiO 3 (PLT) is one of the interesting materials for DRAM applications due to its room temperature paraelectric nature and its higher dielectric permittivity. PLT thin films of different thickness ranging from 0.54- 0.9 w m were deposited on Pt coated Si substrates by excimer laser ablation technique. We have measured the voltage (field) dependence, the thickness dependence, temperature dependence of dc leakage currents and analysis is done on these PLT thin films. Current- voltage characteristics were measured at different temperatures for different thick films and the thickness dependence of leakage current has been explained by considering space charge limited conduction mechanism. The charge transport phenomena were studied in detail for films of different thicknesses for dynamic random access memory applications.

Silicon Surface Chemical Treatments in Oxide/Nitride Dielectric Stack Properties

AbstractOxide/Nitride dielectric stack is widely used as the standard dielectric for DRAM capacitors. The influence of the chemical cleaning prior to the stack formation has been studied in this work. As a result, morphological data such as stack surface roughness (Atomic Force Microscopy) and silicon nitride (SiN) incubation time for growth are comparable for all the studied cases on &lt;Si&gt;. However, Tof-SIMS exhibits different oxygen content at the Si/stack interface following the different chemical treatments. Electrical measurements show comparable C-V and I-V results, for the same Equivalent Oxide Thickness (same capacitance at strong accumulation i.e.-3V) while the different studied interfaces bring different interface states density with lower values for higher interfacial oxygen content. For DRAM applications, a clear improvement in electrical characteristics is obtained under low interfacial oxygen content conditions. Results are compared in embedded-DRAM cells for which we developed an industrially compatible dielectric deposition sequence to obtain minimum leakage current with maximum specific capacitance and no particular linking constraints.

Characteristics of BST Thin Film Prepared by Novel Chemical Solution Deposition Method for High-Density DRAM Application

Characteristics of BST Thin Film Prepared by Novel Chemical Solution Deposition Method for High-Density DRAM Application

Characteristics of BST Thin Film Prepared by Novel Chemical Solution Deposition Method for High-Density DRAM Application

Batium strontium titanate (BST) is an important material for dynamic random access memory capacitor applications. In this work, BST thin films are prepared by the MOD method and metal-BST-metal capacitors are fabricated. The DTA and TGA analysis and FTIR analysis are carried out to study reactions of precusor during the heat-treated process. The increase of the crystallinity of films improves the dielectric constant. A 420nm BST thin film annealed at 750 obtains pure perovskite phase and has a maximum dielectric constant of 628 (at 100 kHz). The relative dielectric permittivity of (Ba x Sr 1- x )TiO 3 with various Ba/Sr ratio is measured and the optimum value of x seems to be 0.6. The leakage current density of the BST thin film is about 0.03 uA/cm 2 at 3V applied voltage.

Photo-induced growth of dielectrics with excimer lamps

The underlying principles and properties of vacuum ultraviolet (VUV) and ultraviolet (UV) radiation (excimer lamps), generated by a dielectric barrier discharge in a rare-gas (Rg) or a mixture of Rg and halogen, are discussed. Compared with conventional sources, these excimer lamps offer narrow-band radiation at various wavelengths from 108–354 nm and over large areas with high efficiencies and high power densities. The variety of available wavelengths offers an enormous potential for new industrial applications in materials processing. Previously, photo-oxidation of silicon, germanium and silicon–germanium and photo-deposition of single- and multi-layered films of silicon oxide, silicon nitride, and silicon oxynitride have been demonstrated by using excimer lamps. This paper reviews the progress on excimer lamp-assisted growth of high dielectric constant (Ta2O5, TiO2 and PZT) and low dielectric constant (polyimide and porous silica) thin films by photo-CVD and sol–gel processing, summarizes the properties of photo-induced growth of Ta2O5 films and discusses the effect and mechanism of low temperature UV annealing with 172 nm radiation. Metal oxide semiconductor capacitors based on the photo-induced Ta2O5 films grown directly on Si at low temperatures exhibit excellent electrical properties. Leakage current densities as low as 5.2×10−7 Acm−2 and 2.41×10−7 Acm−2 at 1 MVcm−1 have been achieved for the as-grown Ta2O5 films deposited by photo-induced sol–gel processing and photo-CVD, respectively-several orders of magnitude lower than for any other as-grown films prepared by any other technique. A subsequent low temperature (400°C) UV annealing step improves these to 10−8 Acm−2. These values are comparable to those only previously achieved for films annealed at high temperatures between 600°C and 1000°C. These properties make the photo-induced growth of Ta2O5 layers suitable alternative to SiO2 for high density DRAM application.

A fast pump-down V/sub BB/ generator for sub-1.5-V DRAMs

Based on the study about the previously developed V/sub BB/ generators, a fast pump-down and high-efficiency V/sub BB/ generator with a cross-coupled hybrid pumping circuit 2 (CHPC2) is presented in this paper. CHPC2 takes only the advantages from the previous generators, eliminating the disadvantages. CHPC2 shows a |V/sub BB/|/V/sub CC/ as large as 98% even at low V/sub CC/=0.9 V, strongly ensuring that it is suitable at sub-1.5-V DRAM applications. Moreover, CHPC2 exhibits a better pumping efficiency and a larger pumping current over the previous ones with a wide range of the load resistance at V/sub CC/=1.2 V.