Silicon nanocrystal based memory devices for NVM and DRAM applications

Abstract

Si nanocrystal based devices have shown potential in reducing the operating voltages used in continuous floating gate FLASH devices. We discuss the critical aspects of this technology––nanocrystal formation by CVD, nanocrystal passivation, and HCI/FN mode of operation of non-volatile memory bitcells fabricated using a 0.13 μm CMOS process technology. The superior FN erase characteristics of nanocrystal memory compared to a SONOS device are demonstrated, which enables the use of thicker tunnel oxides in nanocrystal memory devices as required to mitigate READ disturb. It is shown that nanocrystal area coverage of <25% is optimal for effective charge isolation and for 2-bit/cell applications. Finally the potential of this technology for use in a 1-transistor PMOS DRAM cell is discussed.