Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications

Abstract

Threshold voltage (V/sub t/) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-/spl mu/m single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N/sub 2/ implant prior to gate oxidation is important to reduce V/sub t/ roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V/sub t/ roll-off characteristics. Finally, the impact of halo implant on V/sub t/ variation in sub-0.2-/spl mu/m buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V/sub t/ variation in sub-0.2-/spl mu/m single workfunction gate pFET.