Source-drain Leakage Current Research Articles

Single Event Effects in 3.3 kV 4H-SiC MOSFETs due to MeV Ion Impact

In this work, MeV alpha particles generated from an accelerator are used to study single event breakdown (SEB) in 4H-SiC MOSFET samples, rated at 3.3 kV. The samples are exposed to bursts of alpha particles under reverse bias conditions to investigate the SEB sensitivity to ion energy and reverse bias. The energies of alpha particles are chosen to reach different depths in the drift region of the MOSFET devices, and also to penetrate the whole drift region. Forward and reverse characteristics are measured after each exposure, as long as no failures occur, to ensure that the device performance is maintained. The measurements show that no significant effects are observed on the drain-source leakage current, while minor effects on gate behavior can be seen as a function of accumulated fluence. Furthermore, SEB can only be triggered with a reverse bias larger than, or equal to 3 kV. A standard MOSFET cell with a similar rated voltage is also simulated in Sentaurus TCAD to study these effects, using two different models for the incident ion-induced ionization: the Alpha Particle and the Heavy Ion model. Simulations show that the Alpha Particle model cannot induce any device failures even with a 3.5 kV reverse bias, while it is possible to trigger a failure by the Heavy Ion model, where the ionization can be selected. Carrier plasma and internal electric field distributions of the two models are plotted and compared, showing that device failures triggered by a heavy ion are related to the hole injection at epi-substrate interface, in which linear energy transfer (LET) of the particle plays an important role.

High-threshold-voltage and low-leakage-current of normally-off H-diamond FET with self-aligned Zr/ZrO2 gate

Normally-off field effect transistor (FET) is highly required for the safe and energy-efficient operation of power switching system. The hydrogen-terminated diamond (H-diamond) FET possesses outstanding properties whereas it usually shows normally on operation. In this paper, high-threshold-voltage and low-leakage-current of normally-off H-diamond FET was achieved via ZrO2/Zr gate fabricated by thermal oxidation (TO) with merits of non-pollution and simple process. The normally-off operation owed to the work function difference between Zr and H-diamond and the positive fixed charge of ZrO2. The X-ray photoelectron spectroscopy results reveal the ZrO2/Zr gate structure and the stoichiometric composition of Zr to O (1:2). The high threshold voltage (−2.7 V) and low drain-source leakage current (10−8 mA/mm) may be attributed to the Schottky barrier of Zr/H-diamond. Additionally, the gate leakage is suppressed by TO-ZrO2. The subthreshold swing, on-off current ratio and gate oxide capacitance per square centimeter are 161 mV/dec, 108 and 0.37 μF/cm2, respectively. These performances demonstrate that the ZrO2/Zr/H-diamond FET would provide an alternative approach for low power H-diamond FET.

Analysis of electro-chemical RAM synaptic array for energy-efficient weight update

While electro-chemical RAM (ECRAM)-based cross-point synaptic arrays are considered to be promising candidates for energy-efficient neural network computational hardware, array-level analyses to achieve energy-efficient update operations have not yet been performed. In this work, we fabricated CuOx/HfOx/WOx ECRAM arrays and demonstrated linear and symmetrical weight update capabilities in both fully parallel and sequential update operations. Based on the experimental measurements, we showed that the source-drain leakage current (ISD) through the unselected ECRAM cells and resultant energy consumption—which had been neglected thus far—contributed a large portion to the total update energy. We showed that both device engineering to reduce ISD and the selection of an update scheme—for example, column-by-column—that avoided ISD intervention via unselected cells were key to enable energy-efficient neuromorphic computing.

Simulation Study of Gate-Drain Leakage Current and Density of Polarization Charge at Heterojunction Interface in GaN HEMTs

In previous report, we showed that the source-drain leakage current at off state can be suppressed by thinning the undoped channel layer even if the gate length was reduced to 25 nm in device simulation of AlGaN/GaN HEMT. On the other hand, if the source-drain leakage current can be suppressed, leak current is dominated by the leakage current between the gate and drain. In this report, the source-drain leakage current and the gate-drain leakage current are calculated when drain voltage is until 50 V. When the sufficiently small access resistance is assumed, change of Al composition of barrier has almost no effect in DC characteristics, while the gate-drain leakage is suppressed when Al composition is lower due to lower polarization charge at heterojunction. To use high Schottky barrier height of the gate of AlGaN layer with high Al composition effectively, reduction of the density of polarization charge by using semi-polar-face is proposed.

Impact of switching frequencies on the TID response of SiC power MOSFETs

Different switching frequencies are required when SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are switching in a space environment. In this study, the total ionizing dose (TID) responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz. A significant shift was observed in the threshold voltage as the frequency increased, which resulted in premature failure of the drain–source breakdown voltage and drain–source leakage current. The degradation is attributed to the high activation and low recovery rates of traps at high frequencies. The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.

Nickel Texture Adjustment on Si and Ge and Its Impact on Nickel Silicide and Germanide

Nickel silicide offers advantages over cobalt silicide, but comes along with possible elevated p source-drain leakage currents. In this paper, the effect of deposition temperature on the Ni texture on Si and Ge and its correlation to the silicide and germanide texture is studied for a better control of their properties. A shift from fiber texture to epitaxial Ni growth and an impact on the silicide and germanide texture was found.

A Slew Rate Variation Compensated <inline-formula> <tex-math notation="LaTeX">$2\times$ </tex-math> </inline-formula>VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method

A $2{\boldsymbol \times }$ VDD I/O buffer based on deterministic PVT variation detection algorithms to achieve slew rate compensation is proposed in this brief. By using the P-PVT and N-PVT Variation Detectors consisting of an inverter and a capacitor, the slew rate variation is significantly reduced against the PVT variation. Besides, the source-drain leakage current is reduced by turning off the auxiliary current paths after the charging and discharging transients are completed. The proposed design is implemented using a typical 40-nm CMOS process. The area of the I/O buffer is $0.216 {\times } 0.052$ mm $^{2}$ . Based on post-layout simulations, the slew rate variation is reduced 38.29% after the process, voltage, temperature, and leakage compensation in the worst case.

Radiation tolerant RF-LDMOS transistors, integrated into a 0.[formula omitted] SiGe-BICMOS technology

Mixed signal on-chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with sufficient ruggedness against ionizing radiation and single event burnout. We report on a novel hardening by design approach for radiation tolerant integrated RF NLDMOS transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease TID induced leakage currents the shallow trench isolation (STI) of MOS transistors was replaced by narrow junction isolated regions. For a significant increase of the SEB onset voltage a cascode arrangement consisting of an isolated NMOS and NLDMOS was chosen. The floating NMOS-drain/NLDMOS-source node in the cascode arrangement is always reverse biased which efficiently avoids a turn-on of the parasitic npn bipolar transistor. The rad-hard isolated NMOS/NLDMOS cascode features a breakdown voltage BVDS > 50 V, a maximum cut off frequency fT= 5 GHz and a maximum oscillation frequency fMAX= 14 GHz. In comparison with standard NLDMOS transistors the isolated NMOS/NLDMOS cascode device shows an increase of the SEB onset voltage from 14V to 30V at a linear energy transfer LET of 67.7 MeVcm2/mg and a negligible increase of source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source.

All-ion-implanted planar-gate current aperture vertical Ga2O3 MOSFETs with Mg-doped blocking layer

A vertical β-Ga2O3 metal–oxide–semiconductor field-effect transistor featuring a planar-gate architecture is presented. The device was fabricated by an all-ion-implanted process without requiring trench etching or epitaxial regrowth. A Mg-ion-implanted current blocking layer (CBL) provided electrical isolation between the source and the drain except at an aperture opening through which drain current was conducted. Successful transistor action was realized by gating a Si-ion-implanted channel above the CBL. Thermal diffusion of Mg induced a large source–drain leakage current through the CBL, which resulted in compromised off-state device characteristics as well as a reduced peak extrinsic transconductance compared with the results of simulations.

(Keynote) Gallium Oxide Electronics: Beyond SiC and GaN

Ultrawide bandgap (UWBG) semiconductors, which are defined in terms of a bandgap energy larger than those of SiC and GaN, are getting attention as emerging materials. Gallium oxide (Ga2O3) is one of the typical UWBG materials and has attractive material properties represented by an extremely large bandgap of about 4.5 eV [1]. Furthermore, availability of high-quality, large-area native wafers manufactured from bulk single crystals synthesized by melt growth methods is another important material feature of Ga2O3 [2]. In this talk, I will introduce our state-of-the-art Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) and Schottky barrier diode (SBD) technologies developed for applications to power and harsh environment electronics. The first single-crystal Ga2O3 transistors by means of metal-semiconductor FETs were demonstrated in 2011 [3]. As a result of continuous efforts, we developed lateral depletion-mode (D-mode) Ga2O3 MOSFETs with a gate-connected field plate (FP) [4]. The devices showed a large off-state breakdown voltage of 755 V, a large drain current on/off ratio of over nine orders of magnitude, stable device operation at temperatures up to 300°C, and negligible DC–RF dispersion. A high gamma-ray tolerance was also demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on their output current and threshold voltage. Lateral enhancement-mode Ga2O3 MOSFETs enabling normally-off operation were fabricated by Si-ion implantation doping in an undoped Ga2O3 layer to form source/drain contacts and access regions [5]. The undoped Ga2O3 channel layer that was fully depleted at thermal equilibrium gave rise to positive threshold voltage. A decent on-state drain current of 1.4 mA/mm and a sufficiently large drain current on/off ratio of six orders of magnitude were also achieved. Recently, our FET development took a step forward to vertical D-mode Ga2O3 MOSFETs. In the device structure, the source was electrically isolated from the drain by a current blocking layer formed by Mg-ion implantation except at an aperture opening for drain current conduction. Despite a large source–drain leakage current due to an imperfect function of the current blocking layer, the drain current modulation by applied gate bias was successfully demonstrated. We have also been developing vertical Ga2O3 SBDs. Ga2O3 FP-SBDs were fabricated on n --Ga2O3 drift layers grown by halide vapor phase epitaxy on n +-Ga2O3 (001) substrates [6]. The illustrative device with a net donor concentration of 1.8×1016 cm-3 exhibited a specific on-resistance of 5.1 mΩ·cm2 and an ideality factor of 1.05 at room temperature. Successful FP engineering resulted in a high breakdown voltage of 1076 V. Note that at the breakdown condition, the peak electric field in the Ga2O3 drift layer was estimated to be over 5 MV/cm, which was much larger than theoretical limits for SiC and GaN. Steady and rapid progress has been made on developing building blocks such as bulk wafers, epitaxial films, and device process techniques for realization of Ga2O3 electronics. We fabricated and characterized relatively simple Ga2O3 MOSFET and SBD structures. Both types of developed devices revealed excellent characteristics and thus demonstrated great potential of Ga2O3. Research and development in the next decade is certainly crucial for the road to industrialization of Ga2O3 electronic devices. This work was partially supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: NEDO). [1] T. Onuma, S. Saito, K. Sasaki, T. Masui, T. Yamaguchi, T. Honda, and M. Higashiwaki, Jpn. J. Appl. Phys. 54, 112601 (2015). [2] A. Kuramata, K. Koshi, S. Watanabe, Y. Yamaoka, T. Masui, and S. Yamakoshi, Jpn. J. Appl. Phys. 55, 1202A2 (2016). [3] M. Higashiwaki, K. Sasaki, A. Kuramata, T. Masui, and S. Yamakoshi, Appl. Phys. Lett. 100, 013504 (2012). [4] M. H. Wong, K. Sasaki, A. Kuramata, S. Yamakoshi, and M. Higashiwaki, IEEE Electron Device Lett. 37, 212 (2016). [5] M. H. Wong, Y. Nakata, A. Kuramata, S. Yamakoshi, and M. Higashiwaki, Appl. Phys. Express 10, 041101 (2017). [6] K. Konishi, K. Goto, H. Murakami, Y. Kumagai, A. Kuramata, S. Yamakoshi, and M. Higashiwaki, Appl. Phys. Lett. 110, 103506 (2017).

A robust and area-efficient guard ring edge termination technique for 4H-SiC power MOSFETs

A robust and area efficient adjusted multi-section guard rings (AMS) edge termination structure is employed to a 4H-SiC power MOSFET device rated at 1.7kV and fabricated without extra process steps or masks in this paper. The lightly doped p-type guard ring with adjusted multi-section spacing, which is similar with varied lateral doping technology widely used in silicon edge termination, creates a smoother and more uniform surface electric field distribution across all rings, resulting in a higher reverse blocking voltage with minimal edge termination area. The fabricated AMS-MOSFET devices with an active area of 2.5mm2 have reverse blocking voltage up to 2.5kV at room temperature. Compared to the conventional SiC MOSFETs with the uniform ring spacing, the AMS-MOSFET with the same edge termination area shows more than a 25% increase in the reverse blocking voltage. Furthermore, high-temperature reverse bias stress test is performed to verify junction and termination robustness of the AMS-MOSFET device. A small variation in the reverse blocking voltage and drain-source leakage current are achieved under 168h high-temperature reverse bias stress with the drain bias of 1360V at ambient temperature of 175°C, which suggests an expected robustness in high power application for the fabricated SiC MOSFET with the AMS structure.

Impact of gold deposition parameters on the drain-source leakage current in top-contact pentacene-based thin-film transistors

In this work the influence of gold deposition parameters such as substrate temperature and nominal contact thickness on the drain-source leakage current in top-contact pentacene-based thin-film transistors (TFTs) is investigated. The results reveal that the drain-source leakage current can be suppressed by increasing the substrate temperature and by decreasing the gold contact thickness. It is shown that the observed behavior cannot be fully explained by the standard leakage current model, which attributes the decrease of the leakage current to an increase of the contact resistance. Therefore an extended leakage current model is introduced which takes into account the so-called halo-effect, i.e. the formation of a layer of gold clusters during the gold diffusion process, yielding a parallel resistance between drain and source. It is shown that this model is able to describe both, the dependency of the leakage current on the substrate temperature as well as on the contact thickness.

Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices

Electronic devices consume a large amount of energy globally, and this is projected to accelerate in the near future with greater societal connectivity and cloud storage. To meet power saving goals, both the DC leakage power ( $\text{P}_{\mathrm{ DC}}$ ) and switching AC power ( $\text{P}_{\mathrm{ AC}}$ ) consumption of future electronics must be lowered. Electronic materials play a central role for ultra-low power electronics. To lower the transistor’s gate and source-drain leakage current, high- $\kappa $ dielectric plus metal gate technologies and FinFET structures have been implemented in CMOS. The scaling of supply voltage ( $\text{V}_{\mathrm{ DD}}$ ) is an effective way to lower $\text{P}_{\mathrm{ AC}}$ , where the transistor’s current degradation can be compensated by using high mobility channel materials, such as p-channel Ge, and n-channel InGaAs; high-mobility metal-oxide semiconductors, or two-dimensional (2D) materials. The ultimate $\text{V}_{\mathrm{ DD}}$ reduction is limited by the transistor’s turn-on slope. One proposed solution is the Tunnel FET, where carriers are injected by band-to-band-tunneling directly to the channel. Another method to reach <60 mV/dec turn-on slope is to integrate piezoelectric or ferroelectric materials into MOSFETs. These new electronic materials can also be used for ultra-low power memory application beyond existing DRAM thereby enabling technology for processor-in-memory and brain mimicking chips.

Understanding the dependence of the ohmic drain-source leakage current on gold deposition rate in top-contact pentacene-based thin film transistors

We studied the influence of the gold deposition rate on the drain-source leakage current of top-contact pentacene-based thin film transistors (TFTs) with different channel lengths. It is demonstrated that the anomalous leakage current which occurs only in short-channel TFTs monotonically increases with increasing the gold deposition rate. For TFTs with channel length of 30μm, we also investigated the dependence of the drain-source leakage current on the pentacene grain size as well as the gold deposition rate. It is shown that the pentacene grain size influences the leakage current only in the case if high gold deposition rate is employed, whereas the anomalous leakage current can be avoided by reducing the gold deposition rate. Finally, due to the observed ohmic character of the anomalous leakage current, we propose that the origin of the current can be attributed to parasitic leakage paths on the surface of the pentacene layers formed by the lateral diffusion of gold clusters from drain/source edges into the channel region during gold deposition. Based on this hypothesis, the observed dependence of the anomalous leakage current on the gold deposition rate can be well explained.

Controlling threshold voltage and leakage currents in vertical organic field-effect transistors by inversion mode operation

The interest in vertical organic transistors as a means to overcome the limitations of conventional organic field-effect transistors (OFETs) has been growing steadily in recent years. Current vertical architectures, however, often suffer from a lack of parameter control, as they are limited to certain materials and processing techniques, making a controlled shift of, e.g., the transistor threshold voltage difficult. In this contribution, we present a vertical OFET (VOFET) operating in the inversion regime. By varying the thickness or doping concentration of a p-doped layer in an otherwise n-type VOFET, we are able to shift the threshold voltage in a controlled manner from 1.61 V (for a normal n-type VOFET) to 4.83 V (for the highest doping concentration of 50 mol. %). Furthermore, it is found that low doping concentrations of 20 mol. % can improve the Off state of the VOFET through reduction of the source-drain leakage current.

Reduction of leakage current in In0.53Ga0.47As channel metal-oxide-semiconductor field-effect-transistors using AlAs0.56Sb0.44 confinement layers

We compare the DC characteristics of planar In0.53Ga0.47As channel MOSFETs using AlAs0.56Sb0.44 barriers to similar MOSFETs using In0.52Al0.48As barriers. AlAs0.56Sb0.44, with ∼1.0 eV conduction-band offset to In0.53Ga0.47As, improves electron confinement within the channel. At gate lengths below 100 nm and VDS = 0.5 V, the MOSFETs with AlAs0.56Sb0.44 barriers show steeper subthreshold swing (SS) and reduced drain-source leakage current. We attribute the greater leakage observed with the In0.52Al0.48As barrier to thermionic emission from the N + In0.53Ga0.47As source over the In0.53Ga0.47As/In0.52Al0.48As heterointerface. A 56 nm gate length device with the AlAs0.56Sb0.44 barrier exhibits 1.96 mS/μm peak transconductance and SS = 134 mV/dec at VDS = 0.5 V.

DC characteristics of lattice-matched InAlN/AlN/GaN high electron mobility transistors

Lattice-matched InAlN/AlN/GaN high electron mobility transistors (HEMTs) grown on sapphire substrate by using low-pressure metallorganic chemical vapor deposition were prepared, and the comprehensive DC characteristics were implemented by Keithley 4200 Semiconductor Characterization System. The experimental results indicated that a maximum drain current over 400 mA/mm and a peak external transconductance of 215 mS/mm can be achieved in the initial HEMTs. However, after the devices endured a 10-h thermal aging in furnace under nitrogen condition at 300 °C, the maximum reduction of saturation drain current and external transconductance at high gate-source voltage and drain-source voltage were 30% and 35%, respectively. Additionally, an increased drain-source leakage current was observed at three-terminal off-state. It was inferred that the degradation was mainly related to electron-trapping defects in the InAlN barrier layer.

Monolayer $\hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map

The performance of a 5-nm gate length monolayer MoS2 transistor is benchmarked against an ultrathin body Si transistor of similar dimensions and the ITRS requirements for 2026 low operating power (LOP) technology. The MoS2 transistor has a subthreshold slope of 70 mV/dec, an on -/off-current ratio of 4.8 × 104, a drive current of 238 μA/μm, a peak transconductance of 2.65 mS/μm, a total capacitance of 0.164 fF/μm, and an intrinsic switching delay of 0.276 ps. These numbers for the silicon competitor are 79 mV/dec, 1.8 × 104, 89 μA/μm, 1.22 mS/μm, 0.0733 fF/μm , and 0.331 ps, respectively. The heavier effective mass of the MoS2 significantly reduces the direct source-drain leakage current, and it increases the drive current and the transconductance. The performance metrics of MoS2 transistor are comparable to the ITRS 2026 LOP technology requirements.

Dependence of the DC stress negative bias temperature instability effect on basic device parameters in pMOSFET

To analyze the dependence of the DC stress negative bias temperature instability (NBTI) effect on basic device paraments, such as the channel length, the gate oxide thickness, the doping concentration, we solve the hydrogen molecule drift-diffusion model of NBTI together with the semiconductor device equations. The results are compared with the existing experimental data and the basic laws and physics of devices, which is necessary for reliability studies of NBTI. The analysis results show that NBTI effect is not affected by the channel length change, but maily by the thickness of the gate oxide layer. Gate oxide thickness thinning and gate oxide layer electric field enhancement effect are consistent, which determines the device degradation in the manner of exponential law. With channel doping concentration increasing, NBTI effect will be reduced, which is because the device channel surface hole concentration is reduced, however with the doping concentration increases to such a value that the device source drain leakage current is very low (low leakage device), the MBTI effect is obviously enhanced. These are helpful for understanding NBTI and designing the high performance device.

Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling

We report on thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO2 and HfO2 gate dielectrics. The source–drain leakage current is suppressed by the introduction of an intrinsic region adjacent to the drain, reducing the electric field at the tunnel junction in the off state. We also investigate the temperature dependence of the TFET characteristics and demonstrate that the temperature-induced change in the Si bandgap is the main mechanism that determines the tunneling barrier and hence the drain current ID. We present a model of the TFET as a combination of a gated diode and a MOSFET, which can be solved analytically and can predict the experimentally measured ID over a wide range of drain and gate bias. Finally we report on the low frequency noise (LFN) behavior of TFETs, which unlike conventional MOSFETs exhibits 1/f2 frequency dependence even for large gate areas. This dependence indicates less trapping due to the much smaller effective gate length over the tunneling junction.