A Slew Rate Variation Compensated <inline-formula> <tex-math notation="LaTeX">$2\times$ </tex-math> </inline-formula>VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method

Abstract

A $2{\boldsymbol \times }$ VDD I/O buffer based on deterministic PVT variation detection algorithms to achieve slew rate compensation is proposed in this brief. By using the P-PVT and N-PVT Variation Detectors consisting of an inverter and a capacitor, the slew rate variation is significantly reduced against the PVT variation. Besides, the source-drain leakage current is reduced by turning off the auxiliary current paths after the charging and discharging transients are completed. The proposed design is implemented using a typical 40-nm CMOS process. The area of the I/O buffer is $0.216 {\times } 0.052$ mm $^{2}$ . Based on post-layout simulations, the slew rate variation is reduced 38.29% after the process, voltage, temperature, and leakage compensation in the worst case.