Source-drain Leakage Current Research Articles

(Invited) Vertical Channel Thin Film Transistor: Improvement Approach Similar to Multigate Monolithic CMOS Technology

The silicon based thin film transistors (TFTs) technology evolution is governed by electrical performances that are needed for many applications. Previous papers highlighted the influence of the process, the quality and the nature of the channel material on their electrical properties. TFTs had as well channel parallel to the substrate surface as quasi-vertical channels. This last choice allows an increase of the equivalent current density flowing in the circuit thanks to a shorter channel length and a higher channel width, for the same lithographical node. However, the drain-source leakage current was measured proportional to the source-drain face-to-face area, while Ion is proportional to channel width. This behavior was also observed in vertical monolithic structures. To minimize this effect two main ways are proposed: decreasing the scale, or including a physical barrier between source and drain. We will see that these approaches are really similar to ULSI technology ones.

Growth of InGaN and double heterojunction structure with InGaN back barrier

We study the growth of an InGaN and AlGaN/GaN/InGaN/GaN double heterojunction structure by metal organic chemical vapor deposition (MOCVD). It is found that the crystal quality of the InGaN back barrier layer significantly affects the electronic property of the AlGaN/GaN/InGaN/GaN double heterojunction. A high crystal quality InGaN layer is obtained by optimizing the growth pressure and temperature. Due to the InGaN layer polarization field opposite to that in the AlGaN layer, an additional potential barrier is formed between the GaN and the InGaN layer, which enhances carrier confinement of the 2DEG and reduces the buffer leakage current of devices. The double heterojunction high-electron-mobility transistors with an InGaN back barrier yield a drain induced barrier lowering of 1.5 mV/V and the off-sate source-drain leakage current is as low as 2.6 μA/mm at VDS = 10 V.

TID and Displacement Damage Effects in Vertical and Lateral Power MOSFETs for Integrated DC-DC Converters

TID and displacement damage effects are studied for vertical and lateral power MOSFETs in five different technologies in view of the development of radiation-tolerant fully integrated DC-DC converters. Investigation is pushed to the very high level of radiation expected for an upgrade to the LHC experiments. TID induces threshold voltage shifts and, in n-channel transistors, source-drain leakage currents. Wide variability in the magnitude of these effects is observed. Displacement damage increases the on-resistance of both vertical and lateral high-voltage transistors. In the latter case, degradation at high particle fluence might lead to a distortion of the output characteristics curve. HBD techniques to limit or eliminate the radiation-induced leakage currents are successfully applied to these high-voltage transistors, but have to be used carefully to avoid consequences on the breakdown voltage.

Scaling projections for Sb-based p-channel FETs

Numerical device modeling is used to study p-channel FETs with InSb, GaSb and InGaSb channels. To be as realistic as possible, the basic parameters are chosen to be those measured experimentally in state-of-the-art high-mobility materials, and where possible, predictions are compared against published data. Confinement effects are captured in the simulations using the density-gradient description of quantum transport. The emphasis is on projecting scaling properties and ultimate performance, with key issues being short-channel effects, the importance of source-drain leakage current, power considerations and p +-cap design. Although important, issues related to gate leakage current and gate stack design are not well addressed by modeling, and so are not considered in detail. With III–V complementary circuits and high-speed, low-power applications in mind, the general conclusion is that among the antimonide-based pFETs, InGaSb devices provide the best balance of speed and power dissipation.

Technological dispersion in CNTFET: Impact of the presence of metallic carbon nanotubes in logic circuits

This paper investigates the impact of the metallic nanotube (M-NT) presence within CNTFET circuits: circuit yield and performances are analyzed using calibrated compact models for both the CNTFET and the M-NT. The major cause of technological dispersion in CNTFET technology comes from the control of the carbon nanotube chirality. This lack of control may lead to the presence of metallic nanotubes in the transistor. These M-NTs create shorts which dramatically increase the source–drain leakage current. The random presence and position of M-NT in the ring oscillator circuit is analyzed using Monte Carlo simulation. Two inverter layout configurations are considered in the study and we deduce that a strong improvement in term of yield and power consumption can be obtained using a specific layout configuration where the tubes are shared for the P-CNTFET and the N-CNTFET.

High-Temperature Operation of 50 A (1600 A/cm<sup>2</sup>), 600 V 4H-SiC Vertical-Channel JFETs for High-Power Applications

In this work we have demonstrated the high-temperature operations of 600 V/50 A 4HSiC vertical-channel junction field-effect transistors (VJFETs) with an active area of 3 mm2. Specific-on resistance (RONSP) in the linear region of a single die is less than 2.6 mW.cm2 while the drain-source current is over 50 A under a gate bias (VGS) of 3 V. A reverse blocking gain of 54 is obtained at gate bias ranging from -13 V to -23 V and drain-source leakage current (IRDS) of 200 μA. To demonstrate the use of SiC VJFETs for high-power applications, eight 3 mm2 SiC VJFETs are bonded in a high current 600-V module. RONSP in the linear region of these eight-paralleled SiC VJFETs is 2.8 mW.cm2 at room temperature and increased to 5.35 mW.cm2 at an ambient temperature of 175 °C in air, corresponding to a shift of 0.61%/°C from room temperature to 175 °C. Meanwhile, the forward current is over 360 A at room temperature and reduces to 188 A at 175 °C at drain-source bias (VDS) of 5.25 V and VGS of 3 V.

Predicting Method of Leakage Current in Multiple-Gate Amorphous Silicon TFTs for Active-Matrix Electrophoretic Displays

The large off-state drain-source leakage current of the thin-film transistor (TFT) in active-matrix electrophoretic display (AMEPD) may cause severe crosstalk and long pixel refresh time. Multiple-gate amorphous silicon TFT (a-Si TFT) is a common use to overcome this issue. In this paper, we show that the leakage current of multiple-gate a-Si TFT can be computed from the - characteristics of a single TFT by an analytical current model. The predicted leakage currents show good agreement with the expected values in SPICE simulation. This model is also applicable for the multiple-gate a-Si TFTs used in other high voltage driven devices.

Al0.22Ga0.78N ∕ GaN HFETs Prepared on Vicinal-Cut Sapphire Substrates

heterostructure field effect transistors (HFETs) were prepared on vicinal-cut sapphire substrates. Under reverse bias, it was found that we can achieve smaller gate leakage current and smaller source-drain leakage current by using the 1° tilted substrate. These results could be attributed to the better crystal quality and fewer crystal defects by using vicinal-cut sapphire substrates. With gate length, the maximum transconductance, , was for the HFETs prepared on vicinal-cut sapphire substrates.

Performance of a spin-based insulated gate field effect transistor

Fundamental physical properties limiting the performance of spin field effect transistors are compared to those of ordinary (charge-based) field effect transistors. Instead of raising and lowering a barrier to current flow these spin transistors use static spin-selective barriers and gate control of spin relaxation. The different origins of transistor action lead to distinct size dependences of the power dissipation in these transistors and permit sufficiently small spin-based transistors to surpass the performance of charge-based transistors at room temperature or above. This includes lower threshold voltages, smaller gate capacitances, reduced gate switching energies, and smaller source-drain leakage currents.

AlGaN/GaN/InGaN/GaN DH-HEMTs with an InGaN notch for enhanced carrier confinement

We report an AlGaN/GaN/InGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with high-mobility two-dimensional electron gas (2-DEG) and reduced buffer leakage. The device features a 3-nm thin In/sub x/Ga/sub 1-x/N(x=0.1) layer inserted into the conventional AlGaN/GaN HEMT structure. Assisted by the InGaN layers polarization field that is opposite to that in the AlGaN layer, an additional potential barrier is introduced between the 2-DEG channel and buffer, leading to enhanced carrier confinement and improved buffer isolation. For a sample grown on sapphire substrate with MOCVD-grown GaN buffer, a 2-DEG mobility of around 1300 cm/sup 2//V/spl middot/s and a sheet resistance of 420 /spl Omega//sq were obtained on this new DH-HEMT structure at room temperature. A peak transconductance of 230 mS/mm, a peak current gain cutoff frequency (f/sub T/) of 14.5 GHz, and a peak power gain cutoff frequency (f/sub max/) of 45.4 GHz were achieved on a 1/spl times/100 /spl mu/m device. The off-state source-drain leakage current is as low as /spl sim/5 /spl mu/ A/mm at V/sub DS/=10 V. For the devices on sapphire substrate, maximum power density of 3.4 W/mm and PAE of 41% were obtained at 2 GHz.

Correlation Between Resistivity and Yellow Luminescence Intensity of MOCVD-Grown GaN Layers

AbstractFor further improvements in AlGaN/GaN heterojunction field-effect transistor performance (HFET), it is necessary to reduce the leakage current of the GaN buffer layer. We found a correlation between the leakage current and the intensity of the yellow luminescence of GaN layers taken by UV lamp excitation. The GaN layers were grown by metal organic chemical vapor deposition on SiC substrates. When the samples were excited by a UV (365 nm) lamp, visible yellow luminescence was observed. The leakage current of the GaN buffer layer was measured after deposition of ohmic metal contact. We confirmed clear correlation between the leakage current and the luminescence intensity based from result that the samples with the larger leakage current showed the stronger luminescence intensity. This correlation gives us useful information to understand the drain-source leakage current of AlGaN/GaN HFET.

Increased CMOS inverter switching speed with asymmetrical doping

The DC and transient operations of asymmetrically doped CMOS inverters are investigated. The asymmetrical doping consists of a halo around either the source or the drain. We investigate the DC and transient characteristics of devices and CMOS inverters that contain these halos. To facilitate the investigation, a new algorithm for mixed mode device/circuit simulation is developed. We find that the utilization of the source halo provides significant improvement in the DC and switching characteristics of both devices and CMOS inverters. The drain halo improves performance but gives rise to increased source–drain leakage currents. The effects of narrowing the halo doping is also investigated.

Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10/sup 4/, and the source-drain leakage current is decreased by a factor of 10-10/sup 2/ compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs. >

Radiation effects on fluorinated field oxides and associated devices

Fluorine has been introduced into the LOCOS field oxide by high-energy (2-MeV) F implantation and subsequent annealing at 950 degrees C for 60 min. Improved radiation hardness of the field oxide and its associated device parameters was observed. N-channel MOSFETs isolated by the fluorinated oxide exhibit a lower radiation-induced source-drain leakage current. This is attributed to the smaller density of radiation-induced positive oxide charge in the fluorinated field oxide compared to its control. This is consistent with experimental results showing that threshold voltage shifts of the field-oxide FETs are smaller than their control. In addition, the radiation-induced leakage currents of reverse biased n/sup +/p-junction diodes fabricated with the F implantation process are suppressed, suggesting that the generation of interface traps at the gate SiO/sub 2/-Si and the field SiO/sub 2/-Si interfaces is also reduced in the fluorinated devices. >

Self-Aligned Inversion-Mode lnP MISFET

A self-aligned-gate inversion-mode InP metal-insulator-semiconductor field-effect transistor (MISFET) was successfully fabricated by using plasma-assisted chemical-vapor-deposited Si3N4 film both as the insulator and as the capping layer for the annealing process. A channel mobility of 2700 cm2/Vs and a transconductance of 55 mS/mm at a gate voltage of 4 V were achieved with a reasonably low source-drain leakage current.

Silicon-on-insulator m.o.s.f.e.t.s fabricated on laser-annealed polysilicon on SiO 2

N-channel-enhancement and light-depletion-mode m.o.s.f.e.t.s have been fabricated on laser-annealed 0.5 μm polysilicon films, deposited on 1 μm of SiO2 grown on single-crystal silicon substrates. Threshold voltages of 0.35–0.45 V and −0.5 – −0.7 V and surface mobilities of 170 cm2/Vs and 215 cm2/Vs were obtained on the enhancement and depletion devices, respectively. These results compare favourably with values realised in silicon-on-sapphire (s.o.s.) and bulk N-m.o.s. devices. In addition, the measured source-drain leakage currents match the best reported values for s.o.s. devices.

A CMOS/SOS Synchronous Static RAM Fabricated with an Advanced SOS Technology

A new SOS technology utilizing the non-doped silicon film without any process steps to dope impurities deep into the film under the gate is presented. The minimal junction capacitance is realized even with the shallow junction depth. The small source-drain leakage current is obtained. The threshold voltage is controlled by the film thickness. The simplified process is realized. A 1 K-bit RAM is fabricated with this technology. The access time of the SOS-RAM is faster than that on bulk-silicon by a factor of 1.5 at the same power supply voltage VCC. The shortest access times of 20 ns and 40 ns are measured at VCC=10 and 5 V, respectively. The active power dissipation is 65% of that on bulk-silicon. The quiescent power dissipation of the SOS-RAM is obtained as 30 µW at VCC=5 V.

Semi-Insulating Polycrystalline-Silicon (SIPOS) Films Applied to MOS Integrated Circuits

A semi-insulating polycrystalline-silicon (SIPOS) film doped with oxygen atoms is deposited on the surface of silicon substrates by a chemical vapor reaction of silane and nitrous oxide in nitrogen ambient, and has been studied for the surface passivation of MOS-IC's, in particular, C/MOS-IC's of channel-stopperless structure. SIPOS films are semi-insulating and intrinsically neutral. A double-layer system consisting of 3000 Å SIPOS and 6000 Å SiO2 films is employed as a replacement of a thick silicon dioxide layer in C/MOS-IC's of channel-stopperless structure and exhibits excellent field-passivating properties, namely, a small drain-source leakage current, a high drain breakdown voltage, and a high parasitic threshold voltage. Furthermore, the silicon surface passivated by SIPOS films shows high stability under a severe bias-temperature stress. It is concluded that C/MOS-IC's passivated by SIPOS films are not required to have a channelstopper diffusion region and can be operated at high applied voltages, which leads to higher integrating density and higher reliability.

Comparison of MOS and Metal-Nitride-Semiconductor Insulated Gate Field-Effect Transistors under Electron Irradiation

Insulated gate field-effect transistors with silicon dioxide and silicon nitride insulationwere irradiated with 1 MeV electrons over a wide range of biasing conditions. In nitride insulated devices the radiation induced shift in gate turn-onvoltage was greatly reduced and source-drain leakage currents eliminated. The dependence of the equilibrium shift in gate turn-on voltage on gate bias varied critically with the structure of the insulating layer, and an attempt has been made to correlate this with charge transfer mechanisms across the interfaces of the insulator.