Abstract
This paper investigates the impact of the metallic nanotube (M-NT) presence within CNTFET circuits: circuit yield and performances are analyzed using calibrated compact models for both the CNTFET and the M-NT. The major cause of technological dispersion in CNTFET technology comes from the control of the carbon nanotube chirality. This lack of control may lead to the presence of metallic nanotubes in the transistor. These M-NTs create shorts which dramatically increase the source–drain leakage current. The random presence and position of M-NT in the ring oscillator circuit is analyzed using Monte Carlo simulation. Two inverter layout configurations are considered in the study and we deduce that a strong improvement in term of yield and power consumption can be obtained using a specific layout configuration where the tubes are shared for the P-CNTFET and the N-CNTFET.
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