(Invited) Vertical Channel Thin Film Transistor: Improvement Approach Similar to Multigate Monolithic CMOS Technology

Abstract

The silicon based thin film transistors (TFTs) technology evolution is governed by electrical performances that are needed for many applications. Previous papers highlighted the influence of the process, the quality and the nature of the channel material on their electrical properties. TFTs had as well channel parallel to the substrate surface as quasi-vertical channels. This last choice allows an increase of the equivalent current density flowing in the circuit thanks to a shorter channel length and a higher channel width, for the same lithographical node. However, the drain-source leakage current was measured proportional to the source-drain face-to-face area, while Ion is proportional to channel width. This behavior was also observed in vertical monolithic structures. To minimize this effect two main ways are proposed: decreasing the scale, or including a physical barrier between source and drain. We will see that these approaches are really similar to ULSI technology ones.