MOSFET Drain Research Articles

Analytical Model for the Surrounded Field Plate in Folded Lateral MOSFET Structure

A novel unified analytical model concerning the surrounded plate field is proposed for extended drain MOSFETs (EDMOS) in this article for the first time. The SFP analytical model demonstrates the edge-assisted depletion (AD) effect and the multidimensional AD effect through the dielectric-layer (DL) potential function and 3-D Poisson equation. The closed-form solutions of the electric field and potential distributions are derived to predict the breakdown voltage (BV) for different SFP lengths and dielectric parameters. The 3-D electric field modulation effect brought on by SFP is presented. The impact of SFP parameters on BV is explained using the effective doping concentration ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{N}_{\text{deff}}\text{)}$</tex-math> </inline-formula> . The analytical model takes into account the multidimensional conduction path and the electron accumulation effect while determining the specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{on},\textit{sp}}\text{)}$</tex-math> </inline-formula> of SFP EDMOS. The proposed model is useful for the trade-off between mobility and doping concentration. It can also analyze the impact of the strain on BV and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{on},\textit{sp}}$</tex-math> </inline-formula> . The analytical model is validated by the good agreement between the modeling results and simulation results.

Modeling and simulation of short channel length effect in open drain MOSFET THz detectors

THz radiation detection using FET devices has attracted increasing attention lately. In this paper, we further study a simulated model of FET rectification detection in short channel length. To achieve this, both physics-based analytic model and a detailed TCAD simulation were contacted and compared. The analytical model provided detailed dependence of the response on the channel length below the extension length of the radiation. However, the simulation results were validated by comparison with the experimental data to confirm the validity of the theoretical model. These results present a new model of rectification for short channel lengths and its dependence on the extinction of AC signal through the channel.

DDDMOSFET Performance Improvement by Gate Oxide Removal Followed by Silicided Source/Drain Formation in Gate Slots

In this work, the intentional insertion of slots in metal gate (MG) is introduced to solve the dishing issue for the double-diffused drain MOSFET (DDDMOSFET) fabrication. For traditional DDDMOSFET, the gate oxide layer in slots will be reserved to improve the device reliability, which requires an additional photomask to screen the gate/slot regions during the following sidewall formation and source/drain (S/D) implantation. This makes the process more complicated with increased cost. Without that additional photomask, it is proposed that the removal of gate oxide layer in slots can directly allow the floating S/D formation and the followed Ni silicidation there. It is demonstrated that such a novel process can not only relieve the MG dishing issue but can also effectively result in ~16% higher ON current and comparable OFF current for both N- and P-DDDMOSFETs without threshold voltage shift after applying electrical stress on gates. It is also revealed that the floating silicided S/Ds in slots have negligible influence on device breakdown characteristics. By saving one photomask, this work proposes a novel solution for the effective integration of core devices with very small feature sizes and high-voltage (HV) devices with large feature sizes in the same die, which is a common challenge for display driver chip fabrication using high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> /MG (HK/MG) technology.

Comparative Study of Double Gate and Silicon on Insulator MOSFET by Varying Device Parameters

A comparative study of the single gate MOSFET (SG MOSFET), double-gate MOSFET (DG MOSFET) and silicon-on-insulator MOSFET (SOI MOSFET) is done using MOSFET simulation tool. Device simulation is done by varying different physical parameters of the device structure such as oxide thickness, channel length, temperature and different gate electrodes. Contour plots of SOI and DG MOSFET for electron concentration and potential at initial and final bias are simulated. The drain current vs gate voltage (Id-Vg) characteristics performance simulations show that DG MOSFET is better than SOI MOSFET for different oxide thickness and channel length. It was further noticed that with an increase in the oxide thickness, drain current decreases for DG and SOI MOSFETs. When oxide thickness is reduced from 10 to 7 nm keeping all other parameters same, in DG MOSFET drain current increased by 49.49 % and in SOI MOSFET drain current increased by 66.6 %. When channel length is reduced from 80 to 75 nm in DG MOSFET drain current increased by 1.35 % and in SOI MOSFET drain current increased by 2 %. The performance simulations show that aluminium (Al) gate electrode is better than n+ poly silicon (Si) and tungsten (W) for every MOSFET devices. With respect to aluminium gate electrode in DG MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.89 and 30.5 %, respectively and in SOI MOSFET, for n+ poly Si and tungsten, drain current decreased by 3.84 and 34.61 %, respectively.&#x0D; HIGHLIGHTS&#x0D; &#x0D; Comparative study of Double Gate and Silicon on Insulator MOSFET&#x0D; Simulation of DG and SOI MOSFET using MOSFET simulation tool on nanohub.org&#x0D; Performance analysis of DG and SOI MOSFET by varying different physical parameters like oxide thickness, channel length, temperature and gate electrodes&#x0D; Drain current vs gate voltage (Id-Vg) characteristics performance simulation of DG and SOI MOSFET&#x0D; Contour plot for electron concentration and potential&#x0D; &#x0D; GRAPHICAL ABSTRACT

Contribution to the Control of the Power Switches of DC-DC Converters with two stages of a Photovoltaic System

The work presented in this article proposes the design and the realization of a PWM controller, which allows the control of the power switches of DC-DC converters of discrete two-stage photovoltaic systems in series. The method employed is based on the use of two drivers by exploiting their functionalities in order to improve and control the two power switches of the discretized photovoltaic system. The proposed technique is validated by experimentation on a photovoltaic system, the upper stage of which can request a floating voltage on the MOSFET drain of up to 30V. the studied PV installation is equipped by a protection circuit block for protect the PV equipments in the event of poor connection or deterioration of elements in system blocks. The simulations and the experiments showed a good functioning of the control unit which ensured: An amplitude of the PWM signals large enough to control the power switches, optimal system operation regardless of load and weather changes and good efficiency, and protection of the installation in the event of malfunction.

A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and its Implications for Thin-Dielectric MOSFETs

We derive a complete set of expressions for the MOSFET gate and drain power spectral densities due to elastic and inelastic trapping/detrapping of channel carriers into the gate dielectric. Our calculations explain trapping/detrapping noise (TDN) in various FET operating regions and highlight trap’s position-dependent terms, often neglected in the literature, which are instead important for devices with thin gate dielectrics. Furthermore, we show that TDN has a contribution to the gate current noise, correlated with the drain current fluctuations and we highlight the role of the transfer function between channel charge fluctuations and drain current on the noise characteristics. The model expressions are carefully validated by comparison with 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures (bulk, fully depleted-silicon-on-insulator (FD-SOI), FinFET), channel, and gate materials. Besides shedding new light on TDN, the results could enable trap density extraction from experimental samples with improved accuracy and pave the way to complete and accurate compact models for TDN in MOSFETs.

Study of ΒΕSOI MOSFET Reconfigurable Transistor for Biosensing Application

The Back Enhanced SOI (BESOI MOSFET) is a planar reconfigurable device, which transistor type (n- or p-type) can be programed by the back-gate bias. This transistor is explored in this paper for biosensing application through numerical simulation, based on the fabricated device experimental results. The permittivity value and the charges inside the biomaterial deposited on the underlap region (between gate and source/drain contacts) influence the BESOI MOSFET drain current. The dimensions of the device were evaluated in order to optimize the sensitivity. Among the studied parameters, the underlap length was the most relevant parameter. For short underlap devices, the fringe electric field from the front gate electrode benefits the permittivity-based sensors, while long underlap length devices have a bigger sensitive area in which the charge-based sensor presented better results. Also, the n-type biased device presented higher sensitivity to positively charged materials, while the p-type biased one presented better result for negatively charged materials. The parameters optimization resulted in one order magnitude improvement of the sensitivity for the permittivity-based sensor, for both n- and p-type. As for the charge-based sensor, the optimized device presented twice as bigger sensitivity for the n-type, and at least eight times improvement for the p-type device. This fact represents an advantage of the BESOI structure as the type of the device can be chosen by the back-gate bias.

Hot-Carrier degradation in P- and N-channel EDMOS for smart power application

P- and N- channel Extended Drain MOSFETs (EDMOS) are analyzed through its sensitivity to Hot-Carrier (HC) degradation using accelerated lifetime technique. N- and P- channel EDMOS are optimized for a gate-length LG = 0.5 μm, with gate-oxide thickness at 2.3 nm. We have evaluated more precisely the HC damage caused from channel to the extended drain by an improved extraction of series resistance (ΔRSD) till a 2nd order mobility modeling as a function of stressing VGS from VGS = 0 to VGmax. This allows to determine the worst-case of lifetime dependence in relation to the damage in the drift zone where breakdown sensitivity is found to be intimately bound up with the hot-hole (HH) injection efficiency in N-EDMOS while P-EDMOS exhibits a larger security margin.

On the modelling of temperature dependence of subthreshold swing in MOSFETs down to cryogenic temperature

A comprehensive analysis of the MOSFET subthreshold swing for a 2D subband with exponential band tail of states is first proposed. Then, a compact analytical expression for the subthreshold swing as a function of temperature is derived, well accounting for both its cryogenic temperature saturation and classical higher temperature increase. Moreover, a generalized subthreshold swing calculation applicable to the situation where the MOSFET drain current should be evaluated from the conductivity function within the Kubo-Greenwood formalism is developed.

1.2-kV 4H-SiC SenseFET With Monolithically Integrated Sensing Resistor

A 1.2 kV rated 4H-SiC SenseFET structure with monolithically integrated sensing resistor is proposed and experimentally demonstrated. The SenseFET was fabricated on a 6-inch SiC wafer using the same fabrication process as the conventional MOSFET, where Tungsten-Silicided (WSi2) Poly-Si layer was patterned to form the Poly-Si gate and sensing resistor, ${R}_{S}$ , simultaneously. No impact of the integration of the Sense MOSFET and sense resistor on blocking characteristics was confirmed. Good linearity (within ±10%) of the sense voltage with main MOSFET drain current was observed, independent of drain current level, gate bias voltage, and temperature.

On the DC extraction of the asymmetric parasitic source and drain resistances for MOSFETs

Two different parameter extraction methods are proposed in this article. First, a simple DC method is presented to extract the difference between the drain and source series resistance of MOSFETs. This method is valid for any three- or four-terminal MOSFET and it can be used in linear, triode or saturation region. Second, an integration-based method is proposed to extract the drain resistance and the source resistance of thin-film MOSFETs. Both methods were tested using simulated and measured data of two different devices: zinc oxide (ZnO) and polysilicon TFTs.

A Piecewise Approximation for Short-Channel "Extrinsic" MOSFET Drain Current Dependence on Drain-to-Source Bias Including Linear Triode, Linear Saturation and Asymptotic Saturation Regimes

Previously, we transformed the linear drain bias asymptote equation for the MOSFET drain current in the saturation regime from the “intrinsic” case into “extrinsic” case with accounting for the velocity saturation effect. We obtained the equation for the drain current that yielded the nonlinear dependence on the “extrinsic” drain bias in saturation regime in an implicit form. We derived the equation for the differential conductance of the MOSFET at the “saturation point” and proposed a linear approximation for the dependence of the drain current on the “extrinsic” drain bias in the saturation regime for not very high drain bias when nonlinear effects can be neglected. In this paper, we investigate the asymptotic behavior of the implicit equation for the drain current in case when “extrinsic” drain bias tends to infinity. We propose the nonlinear approximation for the drain current asymptotic that describes a slow current rise to its limiting value when the “extrinsic” drain bias tends to infinity. This approximation is based on analytical solution of quartic equation that can be solved easily enough using Ferrari's method.

Radiation Dose Response of n-Channel MOSFET Submitted to Filtered X-Ray Photon Beam

MOSFET can operate as a radiation detector mainly in high-energy photon beams that are normally used in cancer treatments. In general, such an electronic device can work as a dosimeter from the threshold voltage shift measurements. The purpose of this paper is to show a new way for measuring the dose response of MOSFETs when they are under an X-ray beam generated from a 100-kV potential range, which is normally used in diagnostic radiology. Basically, the method consists of measuring the MOSFET drain current as a function of the radiation dose. For this type of device, it has to be biased with a high-value resistor aiming to see a substantial change in the drain current after it has been irradiated with an amount of radiation dose. Two types of n-channel devices were used in the experiment: a signal transistor and a power transistor. The delivered dose to the device was varied, and the electrical curves were plotted. In addition, a sensitivity analysis of the power MOSFET response was made by varying the tube potential of about 20%. The results show that both types of devices have very similar responses, and the shift in the electrical curve is proportional to the radiation dose. Unlike the power MOSFET, the signal transistor does not provide a linear function between the dose rate and its drain current. We have also observed that the variation in the tube potential of the X-ray equipment produces a very similar dose response.

Vertical GaN-on-Si MOSFETs With Monolithically Integrated Freewheeling Schottky Barrier Diodes

We demonstrate for the first time the monolithic integration of vertical GaN MOSFETs with freewheeling Schottky barrier diodes (SBD), based on a 6.7- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick n-p-n heterostructure grown on 6-inch silicon substrates by metal organic chemical vapor deposition. The anode of the SBD is integrated in the source pad of the MOSFET and the cathode is directly connected to the MOSFET drain through the bottom n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -GaN layer, eliminating the need of any metal wire interconnection. This monolithic integration scheme offers reduced footprint, minimized parasitic components, and simplified packaging. The integrated MOSFET-SBD showed enhancement-mode operation with a threshold voltage of 3.9 V, an ON/ OFF ratio of over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> and a dramatic improvement in reverse conduction, without degradation in on-state performance from the integration of the SBD. The integrated GaN-on-Si vertical SBD exhibited excellent performance, with a specific on-resistance of 1.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a turn-on voltage of 0.76 V, an ideality factor of 1.5, along with a breakdown voltage of 254 V.

Radiation dose response of N channel MOSFET submitted to filtered X-ray photon beam

MOSFET can operate as a radiation detector mainly in high-energy photon beams, which are normally used in cancer treatments. In general, such an electronic device can work as a dosimeter from threshold voltage shift measurements. The purpose of this article is to show a new way for measuring the dose-response of MOSFETs when they are under X-ray beams generated from 100kV potential range, which is normally used in diagnostic radiology. Basically, the method consists of measuring the MOSFET drain current as a function of the radiation dose. For this the type of device, it has to be biased with a high value resistor aiming to see a substantial change in the drain current after it has been irradiated with an amount of radiation dose. Two types of N channel device were used in the experiment: a signal transistor and a power transistor. The delivered dose to the device was varied and the electrical curves were plotted. Also, a sensitivity analysis of the power MOSFET response was made, by varying the tube potential of about 20%. The results show that both types of devices have responses very similar, the shift in the electrical curve is proportional to the radiation dose. Unlike the power MOSFET, the signal transistor does not provide a linear function between the dose rate and its drain current. We also have observed that the variation in the tube potential of the X-ray equipment produces a very similar dose-response.

Scalable [formula omitted]-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design

Analytical circuit design, optimization, characterization and development of design methodology for digital circuits using nanoscale CMOS devices require compact equations. Such equations need to include first order short channel phenomena relevant to the nanoscale technology nodes being used. The present paper demonstrates that α-power model can be updated to include velocity overshoot necessary to characterize devices at ultradeep submicron technology nodes. Further, the three α-power model parameters (velocity saturation index α, transconductance parameter K1 and threshold voltage Vth) expressing MOSFET drain current has been expressed in terms of predictive technology model (PTM) parameters. Representative basic CMOS cells belonging both to inverter and transmission gate categories have been analytically characterized using the updated α-power model up to ultradeep submicron technology node with BSIM verification. It has been shown that consideration of velocity overshoot is important for accurate prediction below 40nm.

Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application.

This paper reports a detailed analysis of the drain current modulation of a single-drain normal-gate n channel metal-oxide semiconductor field effect transistor (n-MOSFET) under an on-chip magnetic field. A single-drain n-MOSFET has been fabricated and placed in the center of a square-shaped metal loop which generates the on-chip magnetic field. The proposed device designed is much smaller in size with respect to the metal loop, which ensures that the generated magnetic field is approximately uniform. The change of drain current and change of bulk current per micron device width has been measured. The result shows that the difference drain current is about 145 µA for the maximum applied magnetic field. Such changes occur from the applied Lorentz force to push out the carriers from the channel. Based on the drain current difference, the change in effective mobility has been detected up to 4.227%. Furthermore, a detailed investigation reveals that the device behavior is quite different in subthreshold and saturation region. A change of 50.24 µA bulk current has also been measured. Finally, the device has been verified for use as a magnetic sensor with sensitivity 4.084% (29.6 T−1), which is very effective as compared to other previously reported works for a single device.

EDMOS in ultrathin FDSOI: Impact of the drift region properties

The development of high-voltage MOSFET (HVMOS) is necessary for including power management or radiofrequency functionalities in CMOS technology. In this paper, we investigate the fabrication and optimization of an Extended Drain MOSFET (EDMOS) directly integrated in the ultra-thin SOI film (7nm) of the 28nm FDSOI CMOS technology node. Thanks to TCAD simulations, we analyse in detail the device behaviour as a function of the doping level and length of the drift region. The influence of the back-plane doping type and of the back-biasing schemes is discussed. DC measurements of fabricated EDMOS samples reveal promising performances in particular in terms of specific on-resistance versus breakdown voltage trade-off. The experimental results indicate that, even in an ultrathin film, the engineering of the drift region could be a lever to obtain integrated HVMOS (3.3–5V).

Efficient Single-Switch Boost-Dual-Input Flyback PFC Converter With Reduced Switching Loss

This paper presents an efficient single-switch boost-dual-input flyback power factor correction (PFC) converter. To achieve a high power factor, a boost PFC cell operating in discontinuous conduction mode is presented. A dual-input flyback dc–dc module, which consists of parallel primary windings and serial secondary windings, operating in critical conduction mode is introduced for galvanic isolation and valley-switching operation. In addition, the proposed converter features high efficiency because the input power is equally divided, and some power is directly transferred to the load by the dual-input flyback dc–dc module. The remaining power is stored in dc-bus capacitors, and it is closely related to the holdup time. Moreover, the currents in the leakage inductors are absorbed by the dc-bus capacitors through a snubber diode, and they are reprocessed by the dual-input flyback dc–dc module. Consequently, the peak voltage in the MOSFET drain is clamped, and the total power conversion efficiency is improved. To verify the performance of the proposed converter, the operating principles, steady-state analysis, and experimental results from a 48 V, 100 W prototype are presented.

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current in saturation with respect to increased temperature and reduced supply voltage explains the increased SEU sensitivity of the flip-flop designs. Experimental SEU cross sections from isotropic Americium-241, 5.4-MeV alpha particle show irradiation increases by 30 × on average, and up to orders of magnitude, as a result of increased device temperature and reduced supply voltage.