Scalable [formula omitted]-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design

Abstract

Analytical circuit design, optimization, characterization and development of design methodology for digital circuits using nanoscale CMOS devices require compact equations. Such equations need to include first order short channel phenomena relevant to the nanoscale technology nodes being used. The present paper demonstrates that α-power model can be updated to include velocity overshoot necessary to characterize devices at ultradeep submicron technology nodes. Further, the three α-power model parameters (velocity saturation index α, transconductance parameter K1 and threshold voltage Vth) expressing MOSFET drain current has been expressed in terms of predictive technology model (PTM) parameters. Representative basic CMOS cells belonging both to inverter and transmission gate categories have been analytically characterized using the updated α-power model up to ultradeep submicron technology node with BSIM verification. It has been shown that consideration of velocity overshoot is important for accurate prediction below 40nm.