Co-Design between Semiconductor, Low-Variation Fully-Additive Printed/Flexible Printing and Variation-Tolerant Digital Circuit Design: (Invited Paper)

Abstract

The low carrier mobility of (printed) semiconductors and high variations of the printed/flexible electronic elements are some of the most difficult challenges for the practical realization of complex printed/flexible electronic circuits. Although contemporary circuit designs accommodate some degree of process variations in conventional silicon processes largely by negative feedback, negative feedback is largely inapplicable in printed/flexible electronics. This is because the gain of the transistors is too low in electronic circuits to realize high open-loop gain, but also because negative feedback is inapplicable to digital circuits in the traditional sense. In this paper, we describe the co-design between the first three supply chains of Printed/Flexible Electronics – the co-design between our modified semiconductor, Fully-Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics printing process and a process-variation-tolerant digital circuit design methodology. The first two co-design supply chains pertain to a low-cost screen-printing process while the last co-design chain pertains to the Quasi-Delay-Insensitive asynchronous-logic digital design methodology (vis-a-vis synchronous-logic) that is self-timed, hence virtually tolerant to any variations. We will also delineate our measurements on digital circuit based on codesign of the aforesaid supply chains, depicting the merits of our modified semiconductor, low-variation printing process, and the ensuing functional printed digital circuit.