Drain-induced Barrier Lowering Research Articles

Improving the Performance of a Doping-Less Carbon Nanotube FET with Dual Junction Source and Drain Regions: Numerical Studies

In this paper, a new structure using dual junctions in the source and drain regions is proposed to improve the electronic characteristics of the doping less carbon nanotube FET. To simulate the proposed structure, the Poisson–Schrodinger equation self-consistent solution method through the nonequilibrium Green’s function (NEGF) procedure has been used. The proposed structure is formed by dividing the source and drain regions into two parts with the same lengths and different work function for each part. The simulation results show that the short channel effects (SCEs) including the sub-threshold swing (SS) and the drain-induced barrier lowering (DIBL) are improved. Also, OFF current has a significant reduction, which in turn increases the current ratio. Besides, improving the ambipolar behavior and leakage current are other benefits of the proposed structure.

A unified 2-D model for nanowire junctionless accumulation and inversion mode MOSFET in quasi-ballistic regime

A unified 2-D continuous potential model for cylindrical nanowire junctionless accumulation mode (JAM) MOSFET and conventional inversion mode (IM) MOSFET has been presented in this manuscript. The 2-D Poisson’s equation in cylindrical coordinates is solved analytically with the help of the superposition principle and evanescent mode analysis of the Fourier-Bessel series is performed. Both free and depletion charges are considered in the 2-D Poisson’s equation. The model thus derived is continuous across different operation regimes (depletion and accumulation/inversion) with respect to VGS. Further, a threshold voltage model is also derived from the potential model and an expression of drain-induced barrier lowering (DIBL) is formulated. The short channel drain current model is derived from the potential-based charge model and quasi-ballistic transport velocity model. Furthermore, models for transconductance (gm) and output conductance (gd) is also formulated from the drain current model. A 3-D TCAD tool from CogendaTM has been used to numerically verify our proposed unified analytical model.

Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

In this work, the effect of gate misalignment towards the source and drain ends for 20 nm recessed double gate junctionless field-effect-transistor (R_DGJLFET) have been studied on various digital and analog performance parameters from device to circuit level while setting the simulation set-up using 2D Silvaco ATLAS technology computer aided design (TCAD). With recessed silicon channel, the quantum confinement effects have been considered for channel thickness <7 nm. In comparison to conventional double gate junctionless FET (C_DGJLFET), the device exhibits lesser OFF-current, improved ON-to-OFF current ratio, better subthreshold slope (SS), and lower drain-induced-barrier-lowering (DIBL). Analogically, it has been found that the misaligned gate towards drain affects the digital and analog parameters more severely in comparison to gate misalignment towards the source end. However, the misaligned R_DGJLFET towards the drain end shows robustness in terms of SS and DIBL with smaller variations of ∼10.84% and ∼61.79%, respectively. Moreover, due to very low parasitic capacitances, the device shows lesser variations in different alternating current (AC) performance parameters namely, transconductance generation factor (TGF), unity gain frequency, and gain-bandwidth product in comparison to C_DGJLFET. With gate misalignment towards source the unity gain frequency, and gain-bandwidth improve by ∼9.67% and ∼19.9%, respectively whereas the TGF remains almost unaffected. Furthermore, to ensure the device capability in circuit application a complementary metal-oxide-semiconductor (CMOS) inverter and common-source (CS) amplifier based on R_DGJLFET have been designed. In contrast to C_DGJLFET based counterpart, the R_DGJLFET expresses its suitability for low-power digital applications with better noise margins and smaller short-circuit current in the CMOS inverter. In analog domain, the R_DGJLFET based CS amplifier shows an improved amplification factor of 4.75 in comparison to C_DGJLFET. This paper provides deep insight into the severity of gate misalignment towards source/drain for R_DGJLFET in both digital and analog domains from device to circuit level.

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model.

Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

Cryogenic Temperature and Doping Analysis of Source-to-Drain Tunneling Current in Ultrashort-Channel Nanosheet MOSFETs

This work analyzes the impact of doping concentration on the temperature-dependent subthreshold current and swing saturation due to direct source-to-drain tunneling (DSDT) in short-channel silicon nanosheet (SiNS) metal–oxide–semiconductor field-effect transistors (MOSFETs). Furthermore, their influence on the drain-induced barrier lowering (DIBL) effect is investigated. Special attention is paid to the importance of the Fermi level and the average tunneling energy, whose energetic positions and distance from each other in the band diagram has a significant role in the temperature-dependent saturation behavior of the subthreshold current and swing, as well as the value of DIBL. Furthermore, we model and present with device simulation the existence of two merging subthreshold swings ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit {S}_ {\text {sth}}$ </tex-math></inline-formula> ) and DIBL effects with increasing gate bias at cryogenic temperatures. The merging is achieved by the superposition of the DSDT and thermionic emission (TE) current, which originate from their own dominated and visibly separated gate-bias regions.

Modeling the Short-Channel Effects in Coplanar Organic Thin-Film Transistors

We have developed models for three different short-channel effects [subthreshold-swing degradation, threshold-voltage roll-off, and drain-induced barrier lowering (DIBL)] in coplanar organic thin-film transistors (TFTs) and verified them against the measured current–voltage characteristics of TFTs having channel lengths as small as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5 \mu \text{m}$ </tex-math></inline-formula> . To derive the models, the Schwarz–Christoffel transformation was applied to obtain a complex mapping function that links the coplanar device geometry to an equivalent geometry in a different coordinate system in order to solve Laplace’s equation of the 2-D potential problem. The solution to this potential problem serves as the basis for the definition of the short-channel models, which can be incorporated into any compact dc models for coplanar TFTs that use the TFTs’ threshold voltage and subthreshold swing as input parameters. To verify the model, the channel-length-dependent effects were extracted from technology computer-aided design (TCAD) simulations (transfer characteristics and surface-potential profile) and from measurements performed on organic p-channel TFTs fabricated using high-resolution stencil lithography.

5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}} = {0.6}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T} = {80}\,\,^{\circ }\text{C}$ </tex-math></inline-formula> . The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology.

Abnormal trend in hot carrier degradation with fin profile in short channel FinFET devices at 14 nm node

This study investigates the impact of fin profiles under hot carrier stress, which defines different base widths: wide-base samples with the smallest slope, medium-base samples, and narrow-base samples with a larger slope. The performance of the narrow samples is better than the medium samples, regardless of transconductance, on-state current, subthreshold swing or drain-induced barrier lowering, demonstrating that the narrow profile samples’ mobility and gate control are better. In long channel devices, the trend of hot carrier degradation (HCD) is in agreement with previous references, and is dependent on the transverse electric field and the fin shapes. However, this trend does not exist for short-channel devices. Positive bias stress and technology computer aided design simulation are applied for investigation and to clarify the reasons for this abnormal HCD trend. Finally, by fitting the multiple vibrational excitation (MVE) mechanism, the slope of the trend lines in the short channel devices are found to indeed match the bending mode. In other words, the disappearance of the general trend between the HCD and fin profiles is caused by the change in the mechanism in the short-channel device. Because the MVE mechanism is independent from the electric field, the narrow profile fin shape more effectively promotes gate control and better performance without affecting the reliability in short channel devices. These results can provide a clear direction for fin shape designers in the future.

Characterization of fully silicided source/drain SOI UTBB nMOSFETs at cryogenic temperatures

In this paper we present an experimental study of SOI UTBB n-MOSFETs at cryogenic temperatures. The device employs fully silicided source/drain with dopant segregation formed by “Implantation Into Silicide” (IIS) process. The impact of the back-gate (Vback) on the device performance is systematically investigated. The results demonstrate that Vback is essential to tune the threshold voltage Vth. And optimization of Vback values can improve the subthreshold swing (SS), Drain-Induced Barrier Lowering (DIBL), transconductance Gm and mobility at cryogenic temperatures, providing a potential to fulfill the ultra-low power requirement for quantum computing application.

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs for different geometrical configurations of the NSFET. In this script, the DC performance of 3D GAA NSFET is analyzed by varying the device's width and thickness. Moreover, the gate length is scaled from 20 nm to 5 nm to check for the device suitability for continuous scaling in logic applications. The thickness and width of each nanosheet are varied in the range of 5 to 9 nm and 10 to 50 nm, respectively, to analyze the performance dependency on the geometry of the device. The impact of geometry of NSFET on various DC performance metrics like transfer characteristics, sub-threshold swing (SS), on current (ION), off current (IOFF), switching ratio (ION/IOFF), threshold voltage (Vth), and drain induced barrier lowering (DIBL) are studied. On top of that, the device's electrical characteristics are analyzed for a wide range of temperatures from -43oC to 127oC to identify the temperature compensation point and is observed at VGS = 0.55 V and ID = 3.86 × 10-6 A. Furthermore, the vital process parameter, work function variations on transfer characteristics of the device is analyzed. Moreover, the analyses reveal that, for sub -7 nm, the NSFET is a potential device for high performance and suitable for logic applications.

Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

Reverse Blocking GaN High Electron Mobility Transistors with Stepped P-GaN Drain

In this work, a reverse-blocking high electron mobility transistor with stepped p-type GaN drain (SPD RB-HEMT) has been proposed and studied in TCAD Sentaurus. In SPD RB-HEMT, the reverse-blocking capability is achieved by employing a stepped p-type GaN (P-GaN) layer connected with the Schottky metal drain. The stepped P-GaN layer is constituted by four P-GaN steps, and the thicknesses of the first to the fourth P-GaN step are descending from the source to the drain side. Due to the P-GaN/AlGaN/GaN structure, the conduction band of the AlGaN/GaN interface is lifted up. Therefore, the two-dimensional electron gas (2-DEG) channel is depleted, and the reverse current is blocked. On the other hand, when the drain is forward biased, the 2-DEG channel is recovered, and the drain induced barrier lowering (DIBL) effect in stepped P-GaN drain structure can lead to a lower on-resistance of the device. The SPD RB-HEMT exhibits a reverse breakdown voltage of −2209 V and on-resistance of 3.01 mΩ·cm2 in TCAD Sentaurus simulation. Compared with the conventional Schottky barrier drain and planar P-GaN drain RB-HEMTs, the SPD RB-HEMTs have shown the balanced and improved forward and reverse-blocking characteristics.

The impact of channel fin width on electrical characteristics of Si-FinFET

&lt;span&gt;This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W&lt;sub&gt;F&lt;/sub&gt;=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.&lt;/span&gt;

Modeling and characterization of optimal nano-scale channel dimensions for fin field effect transistor based on constituent semiconductor materials

This study aims to design an optimal nano-dimensional channel of fin field effect transistor (FinFET) on the basis of electrical characteristics and constituent semiconductor materials (Si, GaAs, Ge, and InAs) to overcome issues regarding the shrinking of dimensions and ensure the best performance of FinFETs. This objective has been achieved by proposing a new scaling factor, K, to simultaneously shrink the physical scaling limits of channel dimensions for various FinFETs without degrading their performance. A simulation-based comprehensive comparative study depending on four variable parameters (length, width, oxide thickness of the channel, and scaling factor) was carried out. The influence of changing channel dimensions on the performance of each type of FinFET was evaluated according to four electrical characteristics: i) ON-state/OFF-state current (ION/IOFF) ratio, ii) subthreshold swing (SS), iii) threshold voltage, and iv) drain-induced barrier lowering. The well-known multi-gate field-effect transistor (MuGFET) simulation tool for nanoscale MuGFET structure was utilized to conduct experimental simulations under the considered conditions. The obtained simulation results showed that the optimal channel dimensions for the best performance of all considered FinFET types were achieved at a minimal scaling factor K=0.125 with 5 nm length, 2.5 nm width, and 0.625 nm oxide thickness of the channel.

Self-Aligned Double Injection-Function TFT for Deep Sub-Micrometer Channels’ Length—Application to Solution-Processed Indium Gallium Zinc Oxide

We propose and demonstrate self-aligned Double Injection Function Thin Film Transistor (DIF-TFT) architecture that mitigates short channel effects in 200 nm channel on non-scaled insulator (100 nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). In this conceptual design, a combination of ohmic-like injection contact and a high injection-barrier metal allows maintaining the high ON currents while suppressing drain-induced barrier lowering (DIBL) effects. Using an industrial 2-D device simulator (Sentaurus), we propose two methods to realize the DIF concept. We use one of them to demonstrate, experimentally, a DIF-TFT based on solution-processed indium gallium zinc oxide (IGZO). Using molybdenum as the ohmic contact and platinum as the high injection barrier, we compare three transistors’ source-contacts: ohmic, Schottky, and DIF. The fabricated DIF-TFT exhibits saturation at sub 1 V drain bias with only about a factor of 2 loss in ON current compared to the ohmic contact.

The influences of radiation effects on DC/RF performances of L g = 22 nm gate-all-around nanosheet field-effect transistor

In this paper, we carried out detailed technology computer aided design simulations to investigate the radiation effects, e.g. total ionizing dose (TID) and single-event effects (SEEs), on direct current (DC) and radio frequency (RF) characteristics of the gate-all-around (GAA) nanosheet field-effect transistor (FET). The simulation model used is composed of seven-layer stacked GAA nanosheet FET with L g = 22 nm, which was implemented in this study. The open current and the drain-induced barrier lowering of the device are ∼3 mA μm−1 and 47 mV V−1, respectively. The results indicate that the TID have little influence on the DC and RF characteristics when the transistor is working in an open state. During the SEEs simulation, we considered three incident directions for the high energy particle, including the lateral direction of the channels, the vertical direction of the channels and the top of the channels. The influence of the particle injecting along the lateral and vertical directions of the channels shows stronger relation with the distance from the incident point compared to the influence of the particle from the top. Besides, the general influence of the particle injecting along the lateral directions of the channels is higher than the other two directions. The total injected charge of the particle injecting along the lateral direction, along the vertical direction and from the top are 3 fC, 1.4 fC and 2.1 fC, respectively. As compared to the fin FET, the GAA nanosheet has superior RF performances and less sensitivity to TID effect. This work can provide a guideline for the GAA nanosheet devices in aerospace and avionic RF applications.

LoGHeD: an effective approach for negative differential resistance effect suppression in negative-capacitance transistors

A negative capacitance transistor with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design simulation results have validated that the output conductance (G DS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (V TH), sub-threshold swing, switching current ratio (I ON/I OFF), and drain-induced barrier lowering.

Comprehensive performance enhancement of a negative-capacitance nanosheet field-effect transistor with a steep sub-threshold swing at the sub-5-nm node

A nanosheet field-effect transistor (NSFET), which has excellent gate control ability, has been considered as the most attractive key architecture that may replace the FinFET below a 5-nm technology node. In this study, a three-dimensional (3D) technology computer-aided design (TCAD) simulation is carried out to evaluate and compare the performance of a negative-capacitance NSFET (NC-NSFET) with an NC fin field-effect transistor (NC-FinFET). The result shows that under the same structural parameters, the NC-NSFET has a higher on-current- to-off-current ratio (Ion/Ioff), and lower sub-threshold swing (SS) and drain-induced barrier lowering (DIBL) than the NC-FinFET. The analog/radio frequency (RF) performance enhancement of the NC-NSFET shows that the NC-NSFET has higher transconductance (gm) and cutoff frequency (fT) at a lower drain voltage (Vds) than the conventional NSFET has. In addition, a negative correlation between fT and SS, which is determined and verified for the first time, reveals that the NC-NSFET enabling analog/RF performance improvement is attributed to the higher ratio of the drain current to the SS.

Reduction of drain induced barrier lowering by optimization Trimetal- GAA -Si -NW MOSFET in multimedia tools

Reduction of drain induced barrier lowering by optimization Trimetal- GAA -Si -NW MOSFET in multimedia tools

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29 % improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.