Drain Current Equation Research Articles

Subthreshold Drain Current Model of Cylindrical Gate All‐Around Junctionless Transistor With Three Different Gate Materials

ABSTRACTA novel subthreshold drain current model has been developed for a cylindrical gate all‐around junctionless transistor with three different gate materials. The proposed device is built with three gate regions of different work functions that effectively reduce the short‐channel effects caused by quantum mechanical effects. The drain current equation is solved for all three operating regions to investigate the device switching characteristics and minimize the drain‐induced barrier lowering (DIBL), velocity saturation, mobility degradation, and tunneling. It is understood that the triple material gate structure enhances the transport efficiency of the device. The proposed analytical model is validated by comparison with Sentaurus TCAD numerical simulator results and good agreement is found to be achieved.

Low‐frequency noise model development of MoS2 field effect transistor and its analysis with respect to different traps

AbstractIn this paper, an analytical drain current model of double gate MoS2 FET Transistor for low‐frequency noise (LFN) power spectral density is developed, and compared its response with the device simulation of the proposed device structure. The developed low‐frequency noise power spectral density (PSD) model is analyzed with respect to different Trap densities, Oxide thicknesses, and high K‐dielectric materials using the TCAD Device simulation tool. Low‐frequency noise is one of the most important noises in any device since it degrades the device's performance. So, in this paper, we used a unique charge‐control model for analyzing the low‐frequency noise by considering the mobility degradation, trapping, and de‐trapping effects caused by trap densities and device lattice structure. Usually, all the previous studies on drain currents with low frequency are based on fluctuations caused by mobility and carrier variations. In our paper, we even considered the charge density fluctuation to analyze the drain current equation. Using a Charge Control Model, we can compute the parameters like gate capacitance (Cgs, Cgd), channel length modulation, and body effect. While other LFN models like the DC model, small signal model, and hybrid model will focus mainly on the static characteristics of the device such as its DC current–voltage (I‐V) relationship, terminal resistances, and input/output conductance of the devices. All the analytical model results were calibrated with the device simulation and it is observed that both are matches each other. Further, it is observed that with an increase in Trap density, the low‐frequency noise increases and low‐frequency noise is dominant at lower frequencies only (1–10 Hz), and after this frequency range the thermal noise will be the dominant noise factor.

Mathematical Modeling of Drain Current Estimation in a CSDG MOSFET, Based on La2O3 Oxide Layer with Fabrication-A Nanomaterial Approach.

In this work, three-dimensional modeling of the surface potential along the cylindrical surrounding double-gate (CSDG) MOSFET is proposed. The derived surface potential is used to predict the values of electron mobility along the length of the device, thereby deriving the drain current equation at the end of the device. The expressions are used for modeling the symmetric doped and undoped channel CSDG MOSFET device. This model uses Pao-Sah’s double integral to derive the current equation for the concentric cylindrical structure of the CSDG MOSFET. The three-dimensional surface potential estimation is performed analytically for doped and undoped device parameters. The maximum oxidant concentration of the oxide layer is observed to be 4.37 × 1016 cm−3 of the thickness of 0.82 nm for (100) and 3.90 × 1016 cm−3 of the thickness of 0.96 nm for (111) for dry oxidation, and 2.56 × 1019 cm−3 of thickness 0.33 nm for (100) and 2.11 × 1019 cm−3 of thickness 0.49 nm for (111) for wet oxidation environment conditions. Being an extensive analytical approach, the drain current serves the purpose of electron concentration explicitly inside the concentric cylindrical structures. The behavior of the device is analyzed for various threshold conditions of the gate voltage and other parameters.

Understanding synaptic characteristics of nonvolatile analog redox transistor based on mobile ion-modulated-electrolyte thickness model for neuromorphic applications

Linear and symmetric updates of the channel current of the redox transistor are involved in bulk mobile ion motion. In this study, we introduce the concept of a variable effective electrolyte thickness (teff) precisely tuned by gate voltage-driven ions into the drain current equation of a conventional transistor. In order to understand the switching characteristics of a nonvolatile analog redox transistor that serves as an artificial synapse for neuromorphic systems, we developed a physics-based model in MATLAB. The simulated synaptic update curves obtained using identical gate pulses were in good agreement with the fabricated Cu-ion-actuated CuOx/HfOx/WOx redox transistor. We then analyzed the impact of geometrical and material-related parameters on the synaptic behavior, taking into account the ion speed and the degree of allowable electric field through the electrolyte. In addition, we performed Monte Carlo simulation to create a non-uniformly changed teff circumstance. With this, we reproduced the fluctuated update of the channel current every gate pulse, which is occasionally observed experimentally when mobile ions are easily moved randomly. Our simulation results revealed that the redox transistor immune to the unevenly changed teff can be achieved by lowering the ion velocity.

Analytical Modeling of Line-Tunneling TFETs Based on Low-Bandgap Semiconductors

The combination of two techniques: low-bandgap semiconductor and line-tunneling structure is an effective way to achieve the highest on-current in TFETs. In this paper, design of low-bandgap line-tunneling TEFT and its analytical modeling of drain current equation is proposed. The previously suggested drain current equation for the low-bandgap line-tunneling TEFT has been explained in a relatively complex form based on the minimum tunnel path that is an effective factor in determining band-to-band tunneling (BTBT). It has been simplified in this paper and reformulated based on gate-to-source voltage. Important design factors such as source doping concentration, material and thickness of the gate-insulator were examined by simulation and numerical calculations based on the minimum tunnel path for two low-bandgap In0.88Ga0.12As and relatively high-bandgap GaSb semiconductors. The comparison of the results obtained from simulations with the proposed analytical drain current model show a good agreement. Drain doping concentration, is an effective factor on the off-state current of low-bandgap TFET. This factor was examined in order to reduce the off-current.

Analysis and comparison of total resistance models for accurate static modeling of long- and short-channel OTFTs produced with various organic materials

In the present study, long- and short-channel organic thin film transistors (OTFTs) produced with various organic semiconductor materials as active layers were fabricated, characterized, and modeled. Two charge transport models, the Meyer-Neldel rule grain boundary-trapping (MNR-GBT) and variable range-hopping models (VRH), were applied to investigate the total device resistance of different types of OTFTs fabricated with various organic semiconductor materials. A generalized method of assessing the current-voltage characteristics of both short- and long-channel OTFTs fabricated with different materials is also presented. All of the devices are described theoretically in terms of their current-voltage characteristics by considering the total resistance's dependence on the gate voltage, which was calculated by substituting the total resistance into the drain current equation. The calculated and measured total resistance and output current-voltage characteristics of each device are presented. Using the best modeled values for the total resistance, the experimental data of output current-voltage characteristics ID(VD) of different kinds of OTFTs are in agreement with those calculated for four different types of OTFTs with long and short channels. The developed model including the total device resistance (according to the Meyer-Neldel rule grain boundary-trapping model) can be applied to long and short-channel devices produced with different materials generalizing all types of OTFTs.

An ON-Current and Effective Drive Current Model for Nanowire MOSFETs with Random Dopant Fluctuations

We report a novel analytic model for the ON -current and effective drive current in nanowire MOSFETs considering the random dopant fluctuation effects. This model is derived from the basic drain current equation considering RDF in the channel region of the device. The model makes use of appropriate voltage relations to be applied in the oxide-interface boundary conditions, and is found to be in excellent agreement with TCAD simulations of the device considering RDF effects.

An electrostatic analytical modeling of high-k stacked gate-all-around heterojunction tunnel FETs considering the depletion regions

This paper deals with the analytical modelling of high-k stacked Gate-All-Around Heterojunction Tunnel Field Effect Transistor (GAA-HJTFET) considering the depletion regions. The surface potential is derived from 2D Poisson’s Equation using the Parabolic Approximation Methodology and the Electric field is obtained by differentiating the surface potential. The drain current is obtained by considering volume of the device, shortest tunnelling path using the Kane’s Model. Due to heterojunction of the SiGe the energy band of the device move downwards to the intrinsic region because of which ION current improves, supress ambipolar behaviour of the device and reduces subthreshold swing. ION-IOFF ratio obtained from the device is 1010. Threshold voltage, transconductance is calculated using drain current equation where the threshold voltage is between 0.7 and 0.8 V and transconductance is 280 µA/mV. The results obtained are validated using ATLAS TCAD Simulation Tool.

A Review on the Study of Temperature Effects in the Design of A/D Circuits based on CNTFET

In this paper, we review a procedure to study the effects of temperature in the design of A/D circuits based on CNTFETs. At first, we briefly describe a compact model, already proposed by us, in which the temperature variation in the drain current equation and in energy band gap is considered. Then, the effects of temperature variations in the design of analog circuits, such as a cascode current sink mirror and an Operational Transconductance Amplifier (OTA), and in the design of digital circuits including in particular NAND and NOR logic gates, are illustrated and widely discussed.

2D Surface potential and mobility modelling of doped/undoped symmetric double gate MOSFET

The 2D surface potential and mobility models are proposed for symmetric doped/undoped channel double gate FET (DGFET) device. This is then used in drain current equation obtained by combining Pao-Sah's double integral formula with Pierret–Shields' type current model. The surface potential model and mobility model both are analytic and differently solved for both undoped and doped device. Being an explicit and continuous expression, the drain current model is used to describe the behaviour of the device at below and above threshold condition. Simulations are carried out using TCAD Sentaurus bundle of Synopsis tool. The accuracy of the proposed model is analysed and compared with the simulation result for different channel length and channel thickness value of the device.

Classical and quantum charge density model of nano scale doped DG MOSFETs below onset of strong inversion

Classical and quantum inversion charge density models are derived below threshold for a doped double-gate (DG) MOSFET. Since our charge density model includes a 2D analytical solution of channel potential considering the contribution of both mobile charge and doping concentration terms, the proposed models are also investigated slightly above threshold of the device having different channel lengths and validated by 2D TCAD (Technology Computer Aided Design) simulation. Quantum Confinement Effects are incorporated in quantum model by considering a 1D infinite rectangular well with a perturbation applied. Finally charge models are implemented in suitable drain current equation to study the electrical behavior of the device.

Low-power analogue computational blocks based on high-performance floating-gate MOSFET resistor

ABSTRACTThis article proposes a new FGMOS-based programmable FGMOS resistor. A highly linear resistor is implemented by cancelling the non-term present in the drain current equation of MOSFET operating in the linear region. The inherited features of FGMOS resistor are simplicity, programmability, wider bandwidth and very low power dissipation without supply voltage. The power dissipation of the proposed FGMOS resistor is only 985 nW. Analogue computational blocks such as programmable reciprocal circuit, current to voltage converter and low-pass filter as applications of proposed programmable FGMOS resistor are also suggested. The power dissipation of reciprocal circuit and low-pass filter are 14.7 and 131 µW, respectively. To demonstrate the efficacy of the circuits, simulations are carried out using SPICE on 0.13 µm CMOS technology.

A Unified Scalable Quasi-Ballistic Transport Model of GFET for Circuit Simulations

A unified quasi-ballistic transport model is developed for single- and double-gate graphene field-effect transistors (GFETs) using the McKelvey flux theory approach. The proposed model is compact, scalable, and compatible for the simulation of I-V characteristics of GFET for all regions of device operation. The drain current equation (IDS) incorporates the formulation of quasithermal velocity, quasi-ballistic mobility of charge carrier (describe the carrier transport of 2-D material like graphene), and source/drain backscattering coefficient. This model is also capable to describe the mobility of graphene material in degenerate and nondegenerate states. The GFET with different channel lengths, widths, and oxide thicknesses is simulated using this model for single- and double-gate devices. The proposed model synchronized with experimental results and explains the peculiar transport characteristics of GFET with normalized root-mean-square error less than 9%.

Effects of Temperature on Switching Time and Power Dissipation of CNTFET-Based Digital Circuits

In this paper we study the effects of temperature in CNTFETs based digital circuits with particular reference to rise time and gate delay. At first we start from a semi-empirical model of CNTFET, already proposed by us, in which the temperature variation in the drain current equation and in energy bandgap is considered. Then, after a brief analysis of noise margins and static power in NOT logic gates, we analyze the timing performances and transient power dissipation in order to define the optimal working condition for different supply voltages and for different temperatures. The procedure proposed can easily be applied to any other logic gate.

Effects of Temperature in CNTFET-Based Design of Analog Circuits

In this paper we simulate the effects of temperature in CNTFET- based design of analog circuits, enhancing a semi-empirical model of CNTFET, already proposed by us, in which the temperature variation in the drain current equation and in energy bandgap is considered in order to estimate the change in static and dynamic conditions. A short description of the model used to reproduce the I-V characteristics of the device, at different temperatures, is given. Then the effects of thermal variations in the design of a phase shift oscillator, a cascode current sink mirror and an operational trans-conductance amplifier, are illustrated and widely discussed.

Effects of Temperature in CNTFET-Based Design of Digital Circuits

In this paper we simulate the effects of temperature in CNTFETs-based digital circuits, enhancing a compact model, already proposed by us, in which the temperature variation in the drain current equation and in energy bandgap is considered. Using ADS software, we simulate some basic digital circuits including NOT, NOR and NAND logic gates. In particular we observe how typical quantities like noise margin and static power vary in relation to temperature and supply voltage. At last we find that generally the most critical working condition is at high temperatures with some exceptions depending on supply voltage applied.

A Simple Drain Current Model for MOS Transistors with the Lorentz Force Effect.

A novel concept of drain current modelling in rectangular normal MOS transistors with the Lorentz force has been proposed for the first time. The single-drain MOS transistor is qualified as a magnetic sensor. To create the Lorentz force, a DC loop current is applied through an on-chip metal loop around the device, and the relation between the applied loop current and the created magnetic field is assumed to be linear in nature. The drain current of the MOS transistor is reduced with the applied Lorentz force from both directions. This change in the drain current is ascribed to a change in mobility in the strong inversion region, and a change in mobility of around 4.45% is observed. To model this change, a set of novel drain current equations, under the Lorentz force, for the strong inversion region has been proposed. A satisfactory agreement of an average error of less than 2% between the measured and the calculated drain currents under the magnetic field created by an on-chip metal loop is achieved.

A new assessment method of pHEMT models by comparing relative errors of drain current and its derivatives up to the third order

Nowadays, there exist relatively precise pHEMT models available for computer-aided design, and they are frequently compared to each other. However, such comparisons are mostly based on absolute errors of drain-current equations and their derivatives. In the paper, a novel method is suggested based on relative root-mean-square errors of both drain current and its derivatives up to the third order. Moreover, the relative errors are subsequently relativized to the best model in each category to further clarify obtained accuracies of both drain current and its derivatives. Furthermore, one our older and two newly suggested models are also included in comparison with the traditionally precise Ahmed, TOM-2 and Materka ones. The assessment is performed using measured characteristics of a pHEMT operating up to 110 GHz. Finally, a usability of the proposed models including the higher-order derivatives is illustrated using s-parameters analysis and measurement at more operating points as well as computation and measurement of IP3 points of a low-noise amplifier of a multi-constellation satellite navigation receiver with ATF-54143 pHEMT.

TCAD Simulation and Analysis of Drain Current and Threshold Voltage in Single Fin and Multi-Fin FinFET

Objectives: This study involves analysis the characteristics of Tri-gate single and double-fin FinFET. It shows the threshold voltage change due to depletion charges. Further, we investigate the effect of increasing number of fins on drain on-off current Methods/Statistical Analysis: In this work, it characterize leakiest path (minimum potential point in the channel) at weak inversion and strong inversion using analytical model. Here, the drain current equation is modelled by considering the effects of the depletion charges in the channel near the Source/Drain and substrate interface. Later, these results are verified using TCAD simulations. Findings: This model is extended for multi-fin FinFET, for analyzing the effect of increasing the number of fins and varying the thickness of fin on the drain ON (at VGS=VDD) current and drain OFF (at VGS=0) current (Leakage current) of trigateFinFET. Finally, it analyze the corner effect in trigateFinFET and propose a solution to reduce it. Application/Improvement: The increase in Threshold voltage with the inclusion of depletion charges. Also, an order increase in drain ON current with two fins keeping the short channel effects minimized.

Modelling of capacitance and threshold voltage for ultrathin normally-off AlGaN/GaN MOSHEMT

A compact quantitative model based on oxide semiconductor interface density of states (DOS) is proposed for Al0.25Ga0.75N/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT). Mathematical expressions for surface potential, sheet charge concentration, gate capacitance and threshold voltage have been derived. The gate capacitance behaviour is studied in terms of capacitance–voltage (CV) characteristics. Similarly, the predicted threshold voltage (V T) is analysed by varying barrier thickness and oxide thickness. The positive V T obtained for a very thin 3 nm AlGaN barrier layer enables the enhancement mode operation of the MOSHEMT. These devices, along with depletion mode devices, are basic constituents of cascode configuration in power electronic circuits. The expressions developed are used in conventional long-channel HEMT drain current equation and evaluated to obtain different DC characteristics. The obtained results are compared with experimental data taken from literature which show good agreement and hence endorse the proposed model.