Abstract
In this paper we study the effects of temperature in CNTFETs based digital circuits with particular reference to rise time and gate delay. At first we start from a semi-empirical model of CNTFET, already proposed by us, in which the temperature variation in the drain current equation and in energy bandgap is considered. Then, after a brief analysis of noise margins and static power in NOT logic gates, we analyze the timing performances and transient power dissipation in order to define the optimal working condition for different supply voltages and for different temperatures. The procedure proposed can easily be applied to any other logic gate.
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