Double Pulse Test Research Articles

Crosstalk Suppression Method for GaN-Based Bridge Configuration Using Negative Voltage Self-Recovery Gate Drive

In order to suppress the crosstalk in gallium nitride (GaN) based bridge configuration, a novel negative voltage self-recovery gate drive (NVSRGD) is proposed in this article. The resistor–capacitor–diode voltage divider is applied to establish the negative gate–source voltage and suppress the impact of positive crosstalk. The antiparallel diode is added to constitute a low-impedance Miller current path from the driver integrated circuit (IC) to the GaN device. It works together with the self-recovery gate–source voltage to suppress the negative crosstalk, which not only prevents the GaN device from the negative overstresses but also reduces the reverse conduction loss during the dead time. The NVSRGD is composed of a few passive components, which are suitable for integrating into the driver IC. The capacitors and resistors of the NVSRGD are designed to determine the negative voltage level and the restore time. Additive separate negative voltage power supplies or active devices are not needed. The double-pulse test based on GS66508B verifies the effectiveness of the proposed method for suppressing the positive and negative crosstalk of GaN devices.

Independent closed loop control of di/dt and dv/dt for high power IGBTs

As the insulated gate bipolar transistor (IGBT) modules have their own specific characteristic switching forms, their turn-on and turn-off times are changed according to practical applications. For the conventional gate drives, gate resistors are used to adjust the turn-on and turn-off times which change switching losses that have a significant amount in total losses. Collector current rate of change, $di_{C}/ dt$ and collector-emitter rate of change, $dv_{CE}/ dt$ are dependent on each other and they affect operating parameters in high power converters. Relations between current and voltages during the switching transitions are given and effects of the changes in electrical parameters for the operation of IGBT are described. Thereafter, closed-loop gate drive with analog control that performs independent control of $di_{C}/ dt$ and $dv_{CE}/ dt$ of a new generation IGBT module platform for high power applications is proposed. Unlike conventional gate drives, proposed closed-loop drive makes constant $di_{C}/ dt$ possible while $dv_{CE}/ dt$ is decreased to increase the efficiency of the power conversion system. This leads to decrease of the switching losses without changing the electromagnetic interference (EMI), IGBT voltage, and current stresses which are related with the rate of change of collector current. Simulations are performed in a double pulse test circuit in which new package next high power density dual (nHPD$^{2}$) family MBM450FS33F Hitachi dual IGBT with 3300V 450A ratings is modelled.

Comparative Evaluation of Silicon and Silicon-Carbide Device-Based MMC and NPC Converter for Medium-Voltage Applications

The neutral-point-clamped (NPC) converter and the modular multilevel converter (MMC) are among the most popular converter topologies for medium- and high-voltage applications. This article investigates the impact of silicon-carbide (SiC) switches on the performance of MMC and NPC converters for medium-voltage (MV) applications. Furthermore, two different cases of the circulating current control schemes are considered for the MMC configuration. The experimental prototypes of three-level configurations for both of these topologies are developed to compare and analyze their performances. Furthermore, the double pulse test (DPT) setup is constructed to obtain the device loss characteristics of the switching devices. These characteristics are then used to compute the device losses using the derived loss models. Moreover, in order to generalize the results for wide power range of operation, two sets of devices are considered for the loss analysis of the considered converter configurations. The obtained results for conduction and switching losses are compared for both the converter configurations at various loading conditions. These results provide the operating range for the considered converters to achieve reduced converter losses. Finally, a comparative analysis for the selection of converter configuration based on the obtained results is presented.

Characterization and Modeling of SiC MOSFET Modules for High-voltage Applications

This paper presents a detailed characterization and modeling of 6.5kv SiC MOSFET half-bridge module. Based on the equivalent circuit topology, the model parameters are extracted from the data manual and test data, and the behavior model is constructed to describe the static and dynamic characteristics of the device. This paper used behavioral model functions, and carries out parameter extraction and model fitting for new devices. The model is verified by double pulse test under inductive load. The verification results show that the modeling work is correct and effective, it can predict the switching performance of devices in high voltage applications.

Simulation-Assisted Design of a Power Stack for Improving Static Current Sharing Among Three IGBT Modules Connected in Parallel

In this study, cosimulation with Q3D and Simplorer were adopted to design a single-phase power stack with equal output current on three paralleled IGBT modules in high power application, therefore, the derating of total current will be reduced, which can improve the current utilization and power density of power stack. The performance of the designed stack was verified using a double-pulse test (DPT). The circuit used in the DPT regarded the power stack output current as static current, which is a critical index to evaluate current sharing. The static current sharing among the IGBT modules was mainly dependent on the stray inductance of the DC busbar, IGBT modules, and phase output bar (POB), which is used to connect the IGBT modules to load, in parallel paths of the power stack. Cosimulation was performed to determine the stray inductance of the IGBT modules, DC busbar and POB, and a constant-current-slope method was used to verify the inductance. Subsequently, design the shapes of DC busbar and POB for attaining maximum ratio of imbalanced current (MRIC) of the three IGBT modules is within 3% under 200% (2400A) rated current. The cosimulation results indicated that the MRIC of the current paths in power stack were 0.8%. Finally, three IGBT modules and a gate driver were used to construct power stack with 1000V DC link. The experimental results obtained by DPT indicated that the MRIC was 0.9% under 200% rated current, demonstrating the effectiveness of the proposed stray inductance design method.

Hybrid Data-Driven Modeling Methodology for Fast and Accurate Transient Simulation of SiC MOSFETs

To enable fast and accurate models of SiC MOSFETs for transient simulation, a hybrid data-driven modeling methodology of SiC MOSFETs is proposed. Unlike conventional modeling methods that are based on complex nonlinear equations, data-driven artificial neural networks (ANNs) are used in this article. For model accuracy, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$I$</tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V$</tex-math></inline-formula> characteristics are measured in the whole operation region to train the ANN. The ANN model is then combined with behavior-based equations to model the cutoff region and to avoid overfitting the ANN. In addition, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C$</tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V$</tex-math></inline-formula> characteristics are modeled by ANNs with a logarithmic scale for accuracy. The proposed model is implemented and simulated in SPICE simulator SIMetrix. The simulation results are compared with experimental results from a double pulse tester to validate the proposed modeling methodology. The model is also compared with the Angelov model created by the Keysight MOSFET modeling software. The comparison results show that the proposed model is more accurate than the Angelov model. Besides, when compared to the Angelov model, the proposed model requires 30% less computation time when simulating a double pulse tester. In addition, the proposed modeling method also has better adaptability to model different types of SiC MOSFETs.

Suitability of Voltage Sensors for the Measurement of Switching Voltage Waveforms in Power Semiconductors

This paper investigates the effect of voltage sensors on the measurement of transient voltages for power semiconductors in a Double Pulse Test (DPT) environment. We adapt previously published models that were developed for current sensors and apply them to voltage sensors to evaluate their suitability for DPT applications. Similarities and differences between transient current and voltage sensors are investigated and the resulting methodology is applied to commercially available and experimental voltage sensors. Finally, a selection aid for given measurement tasks is derived that focuses on the measurement of fast-switching power semiconductors.

Modeling and Suppression of the Crosstalk Issue Considering the Influence of the Parasitic Parameters of SiC MOSFETs

Due to the extremely fast switching speed of the SiC MOSFET, its crosstalk issue is more serious than that of the Si IGBT. Therefore, in order to ensure the reliability of the SiC MOSFET converters, the crosstalk problem must be solved firstly. Most of the existing crosstalk suppression methods are aimed at decreasing the crosstalk voltage introduced by the parasitic gate-drain capacitance (Miller capacitance), ignoring the influence of other parasitic parameters on the crosstalk voltage, such as the common source inductance, which may also lead to more serious reliability problems. Thus, this paper firstly establishes the mathematical model of the switching process of the SiC MOSFET half-bridge inverter. Then, the effects of various parasitic parameters (the gate-source capacitance, the gate-drain capacitance, the common source inductance, the gate inductance, the drain inductance) on the crosstalk voltage are analyzed and modeled in detail, which is verified by experiments. Based on the analyses and models, a novel crosstalk voltage suppression circuit is proposed, which can not only suppress the crosstalk caused by the gate-drain capacitance, but also solve the crosstalk issue considering the influence of other parasitic parameters, such as the common source inductance. Finally, a double pulse test platform is established to verify the effectiveness of the designed crosstalk suppression circuit under different voltage/current conditions.

-GaO Field Plate Schottky Barrier Diode With Superb Reverse Recovery for High-Efficiency DC–DC Converter

β-Ga2O3 Schottky barrier diodes with field plate (FP-SBDs) are fabricated and their SPICE-compatible model are constructed for double-pulse test circuit and DC-DC boost converter simulations. The reverse recovery time (trr) of the β-Ga2O3 SBD is 8.8 ns and its reverse recovery charge (Qrr) is 8.33 nC when switching from a forward current of 1 A to a reverse bias voltage of 100 V with a di/dt of 400 A/μs, which is analogous with the prediction of our model. Device with the radius of 500 μm was fabricated, a current of 2 A can be obtained at the forward voltage of 2 V, meanwhile, the breakdown voltage is 467 V. The Ga2O3-based converter module after device packaging with TO-220 reveals a comparative efficiency to that of the SiC-based converter under multiple conditions, and reached up to 95.62% at the input voltage of 200 V. The decent performance of Ga2O3 FP-SBD and its DC-DC converter indicates great potential in power application.

Calculation and Experiment of Stray Inductance of PCB Double-Pulse Test Circuit Based on Three-Dimensional Simulation

Calculation and Experiment of Stray Inductance of PCB Double-Pulse Test Circuit Based on Three-Dimensional Simulation

Development of a Device for On-Die Double-Pulse Testing and Measurement of Dynamic On-Resistance of GaN HEMTs

On-die testing can accelerate development of semiconductor devices, but poses certain challenges related to high frequency and high current switching. This paper describes design and development of a tester for double-pulse switching test and measurement of dynamic on-state resistance of unpackaged High-Electron-Mobility Transistors (GaN HEMTs). The tester is capable of switching an inductive load at drain-to-source voltage up to 400 V and drain current up to 10 A. Design challenges resulting from specific properties of GaN HEMTs and on-die measurement are explained, and solutions are proposed. Essential parts of the developed device are described, including low inductance gate-driver and measurement methods. Modified drain voltage clamping circuit for accurate on-state drain voltage measurement is described. The tester is constructed as a printed circuit board, integrated into a probe station. Voltage and current waveforms are measured with oscilloscope and used to calculate the on-resistance. Results of a reference measurement with commercially available packaged transistors are presented. Waveforms measured on experimental unpackaged normally-off GaN HEMT samples are also presented and discussed. The proposed tester device proved to be capable of performing the dynamic on-resistance measurement with satisfactory results.

A Hybrid Active Neutral Point Clamped Inverter Utilizing Si and Ga2O3 Semiconductors: Modelling and Performance Analysis.

In this paper, the performance of an active neutral point clamped (ANPC) inverter is evaluated, which is developed utilizing both silicon (Si) and gallium trioxide (Ga2O3) devices. The hybridization of semiconductor devices is performed since the production volume and fabrication of ultra-wide bandgap (UWBG) semiconductors are still in the early-stage, and they are highly expensive. In the proposed ANPC topology, the Si devices are operated at a low switching frequency, while the Ga2O3 switches are operated at a higher switching frequency. The proposed ANPC mitigates the fault current in the switching devices which are prevalent in conventional ANPCs. The proposed ANPC is developed by applying a specified modulation technique and an intelligent switching arrangement, which has further improved its performance by optimizing the loss distribution among the Si/Ga2O3 devices and thus effectively increases the overall efficiency of the inverter. It profoundly reduces the common mode current stress on the switches and thus generates a lower common-mode voltage on the output. It can also operate at a broad range of power factors. The paper extensively analyzed the switching performance of UWBG semiconductor (Ga2O3) devices using double pulse testing (DPT) and proper simulation results. The proposed inverter reduced the fault current to 52 A and achieved a maximum efficiency of 99.1%.

Intelligent Power Unit Parameters Design and the Influence Analyses

The power unit is mainly responsible for the power converter’s function of the electric vehicle, which converts the DC power from the battery to the AC power to drive the motor. Therefore, the parasitic parameters of the power unit will directly affect the output performance of the vehicle. In this paper, the parasitic parameters of the power unit are analyzed. By using an asymmetric design, the capacitor cost and performance are balanced. Moreover, the structure of the busbar is optimized according to the reasonable theoretical analysis. The simulation comparison before and after the optimization, and the comparison results of the measurement results by the double pulse test, are given to verify the optimization. Additionally, the ESL of the busbar is reduced by 10 nH. The results will offer some references to the power unit design.

A short circuit protection circuit for SiC MOSFET with self-adjustive blanking time

This paper proposed a desaturation (DESAT) short circuit (SC) protection circuit for SiC MOSFET, where a blanking time setting module and an SC detection module are designed. The fall time of the drain-source voltage (VDS) for each switching period of SiC MOSFET is recorded and set as the blanking time for the hard switching fault (HSF) detection in the next switching period. Consequently, the detection delay for HSF is self-adjustive and can respond quickly to the operating state of SiC MOSFET. FPGA and discrete components are used to implement the proposed circuit. The function of the proposed circuit is verified using the double pulse test. The experiment results show that the blanking time automatically increases with the increase of load current. The default detection delay of the proposed protection circuit is set 240ns for HSF and can be adjusted during the subsequent switching period. So in the test under a 400V bus voltage, the detection delay is 240ns for HSF at the first switching period. And for HSF occurs at the second switching period, the detection delay is 200ns adjusted according to the operating state of the first switching period. Meanwhile, the detection delay for fault under load (FUL) is 72ns.

Failure analysis for opening characteristic of high voltage and high-power silicon carbide module

According to the abnormal curve of opening characteristics in the process of double pulse test, the failure of 6.5kV/100A SiC module is judged, and it is preliminarily concluded that the gate of the module is damaged; The failure of the module is located by means of module anatomy, static characteristics test and chip screening test. It is concluded that the failure of the module is caused by the abnormality of two SiC MOSFET chips in the module; The damage of the chip was located by using stereomicroscope, OBIRCH, SEM and other equipment, and the root cause of MOSFET failure was studied by stripping anatomy. The preparation process of the gate and passivation strip on the MOSFET was poor, and the introduction of defects led to the breakdown of the gate unable to withstand high voltage.

Dynamic-Switching Energy Dissipation Behaviors of Cryogenic Power MOSFET at 77 K

To operate a converter at cryogenic temperatures, understanding the characteristics of power semiconductor devices is critical. This paper investigates the temperature and current dependence of the dynamic performance of five types of SiC power MOSFETs at 77 K. The turn-on and turn-off lasting time and the corresponding switching energy loss are extracted from a series of double-pulse tests. The transient peak voltage of cryogenic MOSFETs is lower, but the switching time is higher than the room-temperature ones. Moreover, power-exponential functional relations with the operating currents are found in the experiments. These results obtained lay some technical bases for exploring superconducting power electronics.

(Invited) Understanding Dynamic RDS(on) in GaN Devices

In this article, we expand on the wide body of experimental and theoretical knowledge of charge trapping phenomena in eGaN devices that cause dynamic on-resistance shifting (dRDS(on)). In previous publications, we advanced a first-principles model to explain this effect, based on the physics of hot carrier scattering. The model led to a set of equations to predict dRDS(on) under different operating conditions of drain voltage, junction temperature, switching frequency and current. In addition, the model has led to iterative improvements in device design, culminating in the near elimination of dynamic on-resistance effects in eGaN devices when operated within datasheet limits.Several groups have studied RDS(on) shifts in GaN FETs that result from single switching waveforms such as in the double-pulse test. EPC’s approach has been to quantify RDS(on) over relatively long time intervals, ranging from billions to trillions of switching transitions. This long-term data is more relevant to practical applications. Furthermore, the resistance rise versus time can be fit to a physics-based model equation. Using these fits, dRDS(on) can be projected out to years of continuous operation, providing an invaluable tool for users to assess lifetime against their mission profile.An example of this kind of long-term data and model fits is provided in Figure 1. The data was taken on the EPC2045 (5th generation 100V eGaN FET). The graph on the left shows the evolution of resistance versus time at different switching voltages (all at a junction temperature of 75 °C). Note that for operation below (and including) the datasheet maximum, dRDS(on) is negligible, even when projected out to 10 years of continuous operation. When operated above datasheet VDSmax, RDS(on) growth is observed, and the evolution is in good agreement with the model. The graph on the right shows data at 150V and two different temperatures. The trapping phenomenon is seen to have a negative temperature activation, whereby on-resistance increases faster at lower temperature. This counter-intuitive result is consistent with the physics of hot carrier scattering, because an electron can travel further between scattering events at lower temperature and therefore gain greater kinetic energy in a given electric field. These highly energetic electrons scatter into unintended regions in the device, where they trap and degrade on-resistance.In this work, we expand on previous results with the following new data and analyses: Long-term dynamic RDS(on) data and model fits for 5th generation 100V and 200V eGaN FETs at various temperatures and voltages extending well beyond datasheet limits.High speed measurements of RDS(on) less than 100 ns after a switching transition, seeking out possible trap states that recover on short timescales but may nonetheless increase switching losses. To within our measurement resolution, we find that eGaN FETs switch to a low resistance state instantly, with no evidence for such “fast” dynamic RDS(on) A comparison of hard-switching versus soft-switching. In contrast to some other GaN technologies, we find that eGaN is essentially immune to dRDS(on) under soft-switching conditions, consistent with the underlying physics of hot carrier scattering.A comparison of inductive versus resistive hard-switching. Despite the different loci in current-voltage space traversed during these two types of switches, we find the impact on dRDS(on) to be minor. This result affirms that the simpler resistive hard-switching circuit is an equally valid method to characterize dRDS(on) in eGaN.Effect of switching speed, with transitions ranging from 1-50 ns.Effect of third quadrant operation. Some GaN technologies suffer from adverse trapping effects when operated in reverse conduction, as can occur during dead time or synchronous operation in a dc-dc converter. We see no evidence for these effects in eGaN. Figure 1

A testing method for evaluating shoot-through immunity of IGBTs in an inverter

The shoot-through fault in inverters results from a gate noise voltage of power semiconductor switches including IGBTs. Testing the gate voltage under the high-speed switching event is important to evaluate immunity to the fault as well as to analyze the mechanism of the fault. This paper presents a testing method of shoot-through immunity in a PWM inverter consisting of IGBTs because the conventional double-pulse test can miss the shoot-through fault in the inverter. Theoretical analysis reveals that the N-base charge has influence on the gate-emitter voltage in the IGBT, which disturbs evaluating the shoot-through immunity in the inverter. This implies that IGBTs have a different characteristic from MOSFETs when the double-pulse test is carried out. The testing method introduces an additional pulse into the off-state IGBT to release the N-base charge, the circuit operation of which is the same as the inverter. Experimental results confirmed that the method did not affected by the N-base voltage, so that it is applicable to testing the shoot-through immunity of IGBTs in an inverter.

A Novel Power Loop Parasitic Extraction Approach for Paralleled Discrete SiC MOSFETs on Multilayer PCB

Paralleled discrete SiC MOSFETs lead to high current capability at low costs. Current sharing is a critical issue for paralleling design with significant impacts on switching losses, current stress, and reliability. The mismatches in power loop caused by parasitic components are one of the main causes for unbalanced currents, which need to be fully extracted and compensated for a well-balanced design. Discrete SiC MOSFETs are usually mounted on a multilayer PCB. The power loop parasitic extraction for such a system needs to deal with current sharing among paralleled devices and multilayer current path coupling effects on PCB. With the two effects mixing together, it is difficult to extract the parasitic components for a single branch from such a multidimensional network. State-of-the-art approaches fail to solve the two issues simultaneously or require very strong computation capability. A novel parasite-specific numerical model is created to reveal the unbalanced components in the power loops. A multiport network with multi-input–multioutput (MIMO) analysis is applied to pursue the correlations between branch currents and parasitic elements in both steady-state process and oscillation process. A four-step parameter extraction procedure is introduced to capture the specific parasitics corresponding to particular current mismatch processes. A double-pulse test (DPT) prototype with two paralleled SiC devices is adopted to demonstrate the proposed approach with artificially inserted mismatches. The proposed method achieves excellent accuracy in parameter extractions. The extraction error is only 2.2% for parasitic inductances and less than 5.6% for resistances and capacitances.

Experimental evaluation of medium-voltage cascode gallium nitride (GaN) devices for bidirectional DC-DC converters

Wide bandgap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), exhibit superior physical properties and demonstrate great potential for replacing conventional silicon (Si) semiconductors with WBG technology, pushing the boundaries of power devices to handle higher blocking voltages, switching frequencies, output power levels, and operating temperatures. However, tradeoffs in switching performance and converter efficiency when substituting GaN devices for Si and SiC counterparts are not well-defined, especially in a cascode configuration. Additional research with further detailed investigation and analysis is necessitated for medium-voltage GaN devices in power converter applications. Therefore, the aim of this research is to experimentally investigate the impact of emerging 650/900 V cascode GaN devices on bidirectional dc-dc converters that are suitable for energy storage and distributed renewable energy systems. Dynamic characteristics of Si, SiC, and cascode GaN power devices are examined through the double-pulse test (DPT) circuit at different gate resistance values, device currents, and DC bus voltages. Furthermore, the switching behavior and energy loss as well as the rate of voltage and current changes over the time are studied and analyzed at various operating conditions. A 500 W experimental converter prototype is implemented to validate the benefits of cascode GaN devices on the converter operation and performance. Comprehensive analysis of the power losses and efficiency improvements for Si-based, SiC-based, and GaN-based converters are performed and evaluated as the switching frequency, working temperature, and output power level are in-creased. The experimental results reveal significant improvements in switching performance and energy efficiency from the emerging cascode GaN devices in the bidirectional converters.