A Novel Power Loop Parasitic Extraction Approach for Paralleled Discrete SiC MOSFETs on Multilayer PCB

Abstract

Paralleled discrete SiC MOSFETs lead to high current capability at low costs. Current sharing is a critical issue for paralleling design with significant impacts on switching losses, current stress, and reliability. The mismatches in power loop caused by parasitic components are one of the main causes for unbalanced currents, which need to be fully extracted and compensated for a well-balanced design. Discrete SiC MOSFETs are usually mounted on a multilayer PCB. The power loop parasitic extraction for such a system needs to deal with current sharing among paralleled devices and multilayer current path coupling effects on PCB. With the two effects mixing together, it is difficult to extract the parasitic components for a single branch from such a multidimensional network. State-of-the-art approaches fail to solve the two issues simultaneously or require very strong computation capability. A novel parasite-specific numerical model is created to reveal the unbalanced components in the power loops. A multiport network with multi-input–multioutput (MIMO) analysis is applied to pursue the correlations between branch currents and parasitic elements in both steady-state process and oscillation process. A four-step parameter extraction procedure is introduced to capture the specific parasitics corresponding to particular current mismatch processes. A double-pulse test (DPT) prototype with two paralleled SiC devices is adopted to demonstrate the proposed approach with artificially inserted mismatches. The proposed method achieves excellent accuracy in parameter extractions. The extraction error is only 2.2% for parasitic inductances and less than 5.6% for resistances and capacitances.