Wide bandgap semiconductor devices based on gallium nitride (GaN) and silicon carbide (SiC) are attractive semiconductor technologies for future generation power electronics.Lateral GaN HEMTs have dominated the low voltage arena, while SiC MOSFETs have been the preferred technology for higher voltage applications. Devices based on GaN are regarded as having a strong potential for next generation power electronics owing to their high electron mobility, high thermal conductivity, high critical electric field and very low reverse recovery time. The theoretical high voltage capability of GaN is superior to both SiC and silicon (Si), which has resulted in significant government investment for the development of vertical GaN architectures, with a particular emphasis on thicker epitaxial layers, as well as more reliable substrates. The relative improvement in the development of native GaN substrates over the recent years has encouraged production of homo-epitaxial GaN-on-GaN vertical devices with low defect densities and reduced capacitances. Some major advantages of vertical GaN devices include their design robustness, due to avalanche breakdown capability, as well as their ability to attain higher blocking voltages through appropriate edge termination. One of the major challenges in designing junction terminations in GaN vertical devices is the limitation in selective area ptype doping. Selective area p-type doping in GaN is typically performed via Mg implantation, which is known to have a low activation efficiency as well as limited range of implant energy and dosage. Addressing these limitations requires innovative design of termination structures. Iterative refinement between TCAD modeling and fabrication can facilitate design optimization to improve breakdown potential. Circuit simulation can be used to project the performance of the device in various applications and benchmark its performance against other conventional materials.This paper proposes a vertical GaN diode with a blocking capability of 1.3 kV, acquired through a simple technique of edge termination. The initial device design consists of a very highly doped (2 × 1020 cm−3) p++ capping layer on top of the pGaN layer to facilitate the formation of a low resistance ohmic contact with the anode metal. Four samples differing in p-type doping levels are studied under reverse bias using Sentaurus TCAD (Synopsys). The simulations are used to examine the regions of the device that are highly susceptible to field crowding, leading to design considerations for improved breakdown performance. It is shown both through simulations and empirically, that elimination of the highly doped p++ capping layer allows the lower doped p-type layer to serve as a Junction Termination Extension (JTE). The proposed simplified technique of edge termination is produced by the regulation of charge in the lower doped pGaN layer, and does not require selective area p-type doping, thereby substantially improving the manufacturability. The empirically validated diode characteristics are then exported to a circuit simulator and compared to a similarly-rated commercially available Si ultra-fast diode using a double pulse test (DPT). Comparison of the switching characteristics of both the diodes reveals that the proposed GaN diode shows significantly higher efficiency during reverse recovery.Fig. 1 shows the shows the initial device design under consideration. A TCAD model of this device was then implemented in Sentaurus TCAD (Synopsys). The simulated device structure is shown in Fig. 2. Fig. 2(a) illustrates a magnified view of the drift and pGaN layer, above the substrate, while the mesh structure of the entire device is shown Fig. 2(b). Fig. 3 illustrates simulated and experimental static characteristics of the devices, both in terms of forward conduction, and reverse breakdown. As can be seen in Fig. 3, the model accurately predicts the static characteristics of the device. However, wafers two and three (W2 and W3) have significantly lower pGaN doping than wafer one and wafer four. This would suggest a greater breakdown voltage for wafer 2 and wafer 3. However, as seen in Fig. 3, this was not the case.Further analysis via TCAD reveals that the p++ capping layer is the reason for the premature breakdown of W2 and W3. Fig. 4 shows electric field distribution plots for W3 before and after selective removal of the p++ capping layer. Prior to removal, the electric field is unable to uniformly spread across the junction, as seen in Fig. 4(a). On the contrary, after removal of the p++ capping layer, a more uniform electric field distribution is obtained.These simulated results were validated experimentally as seen in Fig. 5. The p++ capping layer was etched away everywhere except underneath the anode. From Fig. 5, the breakdown potential of the device improves by approximately 50%. Figure 1
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Jan 1, 2023
Haihong Qin + 6
Open Access
