Active Gate Driving Technique for Series Connecting SiC MOSFETs in the Presence of Gate Pulse Delay Mismatch

Abstract

In this article, series connection of SiC MOSFETs has been attempted with the help of an active gate driving (AGD) technique. The gate currents of SiC MOSFETs are actively controlled in such a way that several devices can switch fast (within 50 ns) even in the presence of a moderate amount of gate pulse delay mismatch and jitter in the gate pulse. This enables the AGD’s to share the gate pulse signal information among each other. Such a feature can reduce the cost of the net solution by reducing the number of optical cables required for the gate pulse transmission. In addition to this, the AGD is designed in such a way that fast switching can be achieved even in the presence of moderate parasitic inductance in the layout. The proposed AGD technique is experimentally verified in a double pulse test setup with two and four switching devices in series using 32 A, 1 kV CREE SiC MOSFETs. The experimental results show turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> switching times of 45 and 34 ns, respectively, at 35 A load current. The AGD has also shown 47% reduction in the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> switching losses compared to the passive gate driving technique.