Double-gate MOSFETs Research Articles

Proposal and Analysis of a High Read and Write Noise Margin 6T-SRAM Cell Using Novel Core Insulator Double-Gate (CIDG) MOSFETs

Proposal and Analysis of a High Read and Write Noise Margin 6T-SRAM Cell Using Novel Core Insulator Double-Gate (CIDG) MOSFETs

An analytical I-V model of SiC double-gate junctionless MOSFETs

Silicon carbide(SiC) double gate junctionless metal oxide semiconductor field-effect transistors(DG JL MOSFETs) have attracted significant attention due to their ideal high temperature characteristics and radiation resistance. Therefore, it is meaningful to exploit an I-V model for SiC DG JL MOSFETs. In this article, we make a linear approximation to describe the relationship between the surface mobile charge density and the surface electron concentration of the device. Based on this approximation and using the one-dimensional Poisson’s equation, we solve for the potential distribution of a SiC DG JL MOSFET in the subthreshold region. From this solution, we derived a functional relationship between the surface mobile charge density in the channel and the channel quasi-Fermi potential. Then we successfully developed a unified I-V model for the SiC DG JL MOSFETs. Based on the drain to source current calculation formula, the calculation expressions for the device’s transconductance and output conductance are derived. By comparing our model with the results from the two-dimensional numerical simulation software Silvaco Atlas, our model’s calculations closely match the two-dimensional numerical simulation results from the subthreshold region to the accumulation region. This model has reference significance for SiC DG JL MOSFETs in the high temperature electronic circuit application field.

Achieving Single-Electron Sensitivity at Enhanced Speed in Fully Depleted CCDs with Double-Gate MOSFETs.

We introduce a new output amplifier for fully depleted thick p-channel CCDs based on double-gate MOSFETs. The charge amplifier is an n-type MOSFET specifically designed and operated to couple the fully depleted CCD with high charge-transfer efficiency. The junction coupling between the CCD and MOSFET channels has enabled high sensitivity, demonstrating readout noise of 0.74 e_{rms}^{-}/pix in one pixel charge measurement. We have also demonstrated the nondestructive readout capability of the device. Single-electron and single-photon per pixel counting in the entire CCD pixel array has been made possible through the averaging of ten samples, achieving 0.15 e_{rms}^{-}/pix in a pixel readout time of 2.74ms. We have demonstrated fully depleted CCD readout with better performance than the floating diffusion and floating gate amplifiers available today, in both single and multisampling regimes, boasting at least 6 times the speed of floating gate amplifiers.

Parametric Analysis of Indium Gallium Arsenide Wafer-based Thin Body (5 nm) Double-gate MOSFETs for Hybrid RF Applications.

The electrical behavior of a high-performance Indium Gallium Arsenide (In- GaAs) wafer-based n-type Double-Gate (DG) MOSFET with a gate length (LG1= LG2) of 2 nm was analyzed. The relationship of channel length, gate length, top and bottom gate oxide layer thickness, a gate oxide material, and the rectangular wafer with upgraded structural characteristics and the parameters, such as switch current ratio (ION/IOFF) and transconductance (Gm) was analyzed for hybrid RF applications. This work was carried out at 300 K utilizing a Non-Equilibrium Green Function (NEGF) mechanism for the proposed DG MOSFET architecture with La2O3 (EOT=1 nm) as gate dielectric oxide and source-drain device length (LSD) of 45 nm. It resulted in a maximum drain current (IDmax) of 4.52 mA, where the drain-source voltage (VDS) varied between 0 V and 0.5 V at the fixed gate to source voltage (VGS) = 0.5 V. The ON current(ION), leakage current (IOFF), and (ION/IOFF) switching current ratios of 1.56 mA, 8.49Í10-6 μA, and 18.3Í107 μA were obtained when the gate to source voltage (VGS) varied between 0 and 0.5 V at fixed drain-source voltage (VDS)=0.5V. The simulated result showed the values of maximum current density (Jmax), one and twodimensional electron density (N1D and N2D), electron mobility (μn), transconductance (Gm), and Subthreshold Slope (SS) are 52.4 μA/m2, 3.6Í107 cm-1, 11.36Í1012 cm-2, 1417 cm2V-1S-1, 3140 μS/μm, and 178 mV/dec, respectively. The Fermi-Dirac statistics were employed to limit the charge distribution of holes and electrons at a semiconductor-insulator interface. The flat-band voltage (VFB) of - 0.45 V for the fixed threshold voltage greatly impacted the breakdown voltage. The results were obtained by applying carriers to the channels with the (001) axis perpendicular to the gate oxide. The sub-band energy profile and electron density were well implemented and derived using the Non-Equilibrium Green's Function (NEGF) formalism. Further, a few advantages of the proposed heterostructure-based DG MOSFET structure over the other structures were observed. This proposed patent design, with a reduction in the leakage current characteristics, is mainly suitable for advanced Silicon-based solid-state CMOS devices, Microelectronics, Nanotechnologies, and future-generation device applications.

Investigations on Cylindrical Surrounding Double-Gate (CSDG) MOSFET using AlxGa1-xAs/InP: Pt with La2O3 oxide layer for fabrication.

The Cylindrical Surrounding Double-Gate MOSFET has been designed using Aluminium Gallium Arsenide in its arbitrary alloy form alongside Indium Phosphide with Lanthanum Dioxide as a high-ƙ dielectric material. The heterostructure based on the AlxGa1-xAs/InP: Pt has been used in the design and implementation of the MOSFET for RF applications. Platinum serves as the gate material, which has higher electronic immunity toward the Short Channel Effect and highlights semiconductor properties. The charge buildup is the main concern in the field of MOSFET design when two different materials are considered for fabrication. The usage of 2 Dimensional Electron Gas has been outstanding in recent years to help the electron buildup and charge carrier accumulation in the MOSFETs regime. Device simulation used for the smart integral systems is an electronic simulator that uses the physical robustness and the mathematical modeling of semiconductor heterostructures. In this research work, the fabrication method of Cylindrical Surrounding Double Gate MOSFET has been discussed and realized. The scaling down of the devices is essential to reduce the area of the chip and heat generation. By using these cylindrical structures, the area of contact with the circuit platform is reduced since the cylinder can be laid down horizontally. The coulomb scattering rate is observed to be 18.3 % lower than the drain terminal when compared to the source terminal. Also, at x = 0.125 nm, the rate is 23.9 %, which makes it the lowest along the length of the channel; at x = 1 nm, the rate is 1.4 % lesser than that of the drain terminal. A 1.4 A/mm2 high current density had been achieved in the channel of the device, which is significantly larger than comparable transistors. The conventional transistor occupies a larger area than the proposed cylindrical structures transistor and is also efficient in RF applications.

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Impact of underlap layer is analytically investigated on asymmetric junctionless dual material double gate MOSFET (AJDMDG) to reduce subthreshold slope and threshold voltage, which are two essential requirements with shrinking device dimensions to avoid short channel effects. The model utilizes two-dimensional Poisson’s equation with parabolic approximation for determining electrical parameters where dimensional ranges are kept within fabrication limit. Excellent accuracy is found for the obtained analytical outcome, when compared with results obtained from TCAD ATLAS simulator. Comparative study is extended for conventional junctionless DMDG (JDMDG) and underlap asymmetric junctionless single material DGFET (UAJDG) device, having identical dimensional parameters and biasing ranges; where the present structure exhibits superior performance in terms of threshold voltage, subthreshold slope and DIBL of 34.57%, 62.85% and 69.85% respectively compared to JDMDG and 12.50%, 26.08% and 40.25% respectively w.r.t UAJDG structure. Supremacy of the proposed architecture is further established with RF/analog Figures of Merit (FOMs), which are essential for designing low power analog amplifier.

Impact of deep cryogenic temperatures on gate stack dual material DG MOSFET performance: Analog and RF analysis

By understanding the potential benefits of Gate Stack Dual Material double gate MOSFET (DG MOSFET), this research aims to contribute to the investigation of its electrical characteristics with improved performance and dependability. A detailed investigation is conducted into the temperature dependent electrical properties at different temperatures. A detailed analysis is conducted on the enhanced gate controllability in lower technology nodes and the protection against short channel effects. Together with the DC performances, this research also analyzes the suggested device's analog performance. The device's performance matrix was presented for temperatures ranging from 70 K to 800 K. The results showsthe improvement the drain current, transconductance, and transconductance generation factor(TGF) with decrease in temperature.

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

The purpose of this study is to investigate the possibilities of the junction-less double-gate (JLDG) MOSFET structure with gallium nitride (GaN) channel material to overcome the limitations of conventional MOSFET structures in improving device performance at scaled gate lengths and voltages. The design targets of this study are the doping profile (ND), and gate work function (Ф). The device has been modeled using the Silvaco Atlas 2D device simulator. The proposed model has been validated by calibrating it against the parabolic potential-based analytical model for short-channel JLDG MOSFETs in the subthreshold regime of Jazaeri et al. Device figure of merits (FOMs) such as ON-current (ION), ON-OFF current ratio (ION/IOFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) have been evaluated. The maximum on-current, (ION) = 0.9 mA/μm, has been achieved by tuning the channel doping concentration (ND) to 1 × 1019 cm−3. Tuning the gate work function, (Ф) also has a substantial effect on the behavior of the device. The lowest OFF-state current (IOFF) of 1.24 × 10−16 A/μm and power dissipation of 9.69 × 10−17 W/μm have been found for gate work-function (Ф) = 5.1 eV (Au). In addition, the on-current to off-current ratio (ION/IOFF) of 7.56 × 1012 revolutionizes the applicability of the device in the semiconductor industry. Thus, the remarkable improvements in device FOMs prove that GaN-based JLDG MOSFETs are a strong contender for applications requiring low-power logic switching in the next generation.

PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation

We introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing the drain current as in the PSP model, we employ a quadratic symmetric polynomial interpolation of the charge in the channel. This eliminates the need for cumbersome derivatives, simplifications, and intricate coding when integrating into a circuit simulator, thereby preventing singularities during numerical iterations. Moreover, thanks to its mathematical formulation equivalent to PSP, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. We validate the accuracy of the model through comparisons with numerical solutions and experiments from the literature.

Correction to: Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node

Correction to: Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node

Spacer effects on the performance of MoTe2/MoSe2 and MoTe2/WSe2 heterostructure double gate MOSFET

In this work, the spacer effects (both low and high-k) on the dc and noise characteristics of heterostructure molybdenum ditelluride (MoTe2/MoSe2 and MoTe2/WSe2) double gate (DG) MOSFET is analyzed. To study the device characteristics, a hybrid methodology that uses both QuantumWise ATK and Sentaurus TCAD tool is used. The performance metrics of the device such as on-current (Ion), Ion/Ioff ratio, subthreshold swing (SS), threshold voltage are obtained. The noise performance of the device is also studied (with/without spacer) using impedance field method. Noise parameters such as noise power spectral density (SID) and noise figure (function of both frequency and bias) has also been simulated and noise components such as G-R noise, flicker noise and white noise are obtained. The simulation results shows that the introduction of spacer material enhances the dc performance of the device and influences its noise characteristics.

Design and analysis of logic circuits based on 8 nm double gate MOSFET

Design and analysis of logic circuits based on 8 nm double gate MOSFET

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Inverter and Universal Gates Implementation Using Novel Core Insulator Double Gate (CIDG) MOSFETs

The Core Insulator Double Gate (CIDG) MOSFET has been explored for digital applications in which the presence of core insulator diminishes the bulk conduction and reduces the off state current. The drain currents of n- and p-type CIDG MOSFETs are matched by tuning gate work functions to deliver the symmetrical pull-up and pull-down characteristics. The inverter and universal logic gates (NAND and NOR) have been designed and implemented to show the usability of the CIDG MOSFETs for digital applications. The DC and transient characteristic of the inverter along with Static Noise Margin (SNM) and time delay parameters have been examined. The designed Inverter shows steeper voltage transfer characteristics, reduced short circuit power dissipation and improved noise immunity. The CIDG MOSFET based NAND and NOR gate implementation and validation by transient analysis have been shown for the first time to the best knowledge of the authors. Also, the rise and fall times of the inverter, NAND and NOR gates have been found to be improved as compared to the DG MOSFET counterparts. The present analysis establishes that CIDG MOSFETs are useful in designing digital circuits with improved performance.

Analysis of Lanthanum Oxide Based Double-Gate SOI MOSFET using Monte-Carlo Process.

This work proposes a Double-Gate (DG) MOSFET with a Single Material made of Silicon On-Insulator (SOI). The Lanthanum Oxide material with a high k-dielectric constant has been used as an interface between two gates and the channel. The Monte Carlo analysis has been used to determine the Conduction Band Energy (Ec) profiles and electron sheet carrier densities (ns) for a Silicon channel thickness (tsi) of 10 nm at 0.5 V gate drain-source voltages. The transverse electric fields are weak at the midchannel of DG SOI MOSFETs, where quantum effects are encountered. The Monte Carlo simulation has been confirmed to be effective for high-energy transport. A particle description reproduces the granularity property of the transport for nanoscale modeling. This work utilizes a Monte Carlo (MC) Simulation for the proposed Double Gate Single Material Silicon On Insulator MOSFET with (La2O3=2 nm) as dielectric oxide on upper and lower gate material. The electrical properties of the DG SOI MOSFETs with Lanthanum Oxide were analyzed using Monte Carlo simulation, including the conduction band energy, electric field, potential distribution, particle movement, and average velocity. The peak electric field (E) simulation results and an average drift velocity (υavg) of 6Í105 V/cm and 1.6Í107 cm/s were obtained, respectively. The conduction band energy for the operating region of the source has been observed to be 4 % to the drain side, which obtained a value of -0.04 eV at the terminal end. This proposed patent design, such as double-gate SOI-based devices, is the best suggestion for significant scalability challenges. Emerging technologies reach the typical DG SOI MOSFET's threshold performance when their geometrical dimensions are in the nanometer region. This device based on nanomaterial compounds has been more submissive than conventional devices. The nanomaterials usage in the design is more suitable for downscaling and reducing packaging density.

ADVANCEMENT IN NANOSCALE ELECTRONICS IN MOSFET

This research explores a novel approach for designing Cylindrical Surrounding Double-Gate (CSDG) MOSFETs with nanometer-scale precision through a layer- by-layer fabrication technique. Traditional top- down methods, such as photolithography and ion beam deposition, are widely used for semiconductor design but present challenges in creating complex heterostructures. In response, this study proposes an alternative method focusing on cylindrical structures to develop high- resolution morphological designs of CSDG MOSFETsThe research emphasizes the versatility of the proposed method, allowing the design of various cylindricalstructures with distinct properties, including periodic and non-periodic arrangements, symmetric andasymmetric configurations, and nanometer-scale gaps/dots. The focus is on the development of a symmetricCSDG MOSFET concerning the center core, providing valuable insights for fabricating structures over thecore of 2D Electron Gas (2DEG). Keywords— Cylindrical Surrounding Double-Gate MOSFET, Fabrication Steps Layer-by-Layer Approach Semiconductor Devices,Nanoscale Electronics ,Transistor Design ,Oxidation Process, Scalability, Simulation ,Oxidant Concentration.

A unified core model of double-gate and surrounding-gate MOSFETs for circuit simulation

This paper presents a new core compact model of double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs for circuit simulations. The current and the terminal charges are continuous with high computation efficiency and accuracy. Despite its accuracy, it retains the same simplicity of the industry standard transistors models. The drain current is worked out without invoking the charge-sheet approximation exploiting a quadratic symmetric polynomial interpolation of the charge in the channel. Apart this clear approximation, no other simplification is used to work out the drain current, the terminal charges, the potential, and electric field in the channel. The accuracy of the model is shown by comparison with the exact numerical solution and experimental data of the literature.

Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes

Circular Double Gate Transistors (CDGTs) is one of the alternative layout-based solutions to mitigate the short-channel effects with superior electrostatic controllability. In this article, TCAD based analysis of the CDGT at the 7 nm node for low-power (LP) applications is carried out and extracted electrical characteristics. The proposed CDGT device offers outstanding performance with ON current of 5.5 × 10−4 Amps, an OFF current of 5.9 × 10−12 Amps, and a corresponding switching ratio of 9.3 × 107 at 300 K. Furthermore, this study examined the performance of CDGT on device geometry by scaling of the gate length from 20 nm to 12 nm and Si thickness variation in the range of 5 nm–8 nm. Additionally, the influence of temperature variation is also studied on CDGT and extracted the temperature compensation point (TCP). Moreover, this simulation illustrates the use of CDGT devices for high switching applications with excellent ON current for lower sub 7 nm technology nodes.

Effect of specularity parameter and convective coefficient on heat transport in semiconductor devices based on mesoscopic method

The effects of thermal behavior on nanoscale Metal Oxide Semiconductor Field Effect Transistor (nano-MOSFET) are still being studied by the semiconductor industry. This study investigates the heat diffusion inside double-gate (DG) and nano-conventional MOSFETs. Simulations of conventional and DG MOSFET are carried out using mesoscopic model lattice Boltzmann method (LBM) coupled with specularity parameter and convective heat transfer coefficient. The simulation results show that the specularity parameter and convective heat transfer term have important role to reduce hotspots in nano-devices. Temperature decreases when the specularity parameter and convective term increase. The temperature reaches 326.76 K for p = 0.1 while for p = 0.4 estimated 320.79 K at the same Rth−1=1010 W/(m2⋅K) in traditional device at t = 30 ps whereas the temperature in the double gate transistors reached 326.28 K and 321.48 K for p = 0.4 and 0.8, respectively. In addition, it is found that the conventional device compared with the double gate device is more heat stability.

Electrical Characterization of Multi-Gate MOSFET with Reduced Short-Channel Effects for High-Power Applications

The double-gate MOSFET is proposed for high-voltage and high-power applications with decreased short-channel effects (SCEs) and drain current with gate overlap. This model explicitly incorporates the SCEs for thin-layered MOSFETs with large drain regions. The device’s short-channel effects are decreased through the drain-resistance effect present in the device. The gate contact overlapped region significantly affects the device operation for high-voltage FETs. These effects are modeled by self-consistent solutions of available multigate MOSFET device models with potential distribution. The demonstrated model can be further applied for size limitations in the modeling of multigate MOSFETs.