Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes

Abstract

Circular Double Gate Transistors (CDGTs) is one of the alternative layout-based solutions to mitigate the short-channel effects with superior electrostatic controllability. In this article, TCAD based analysis of the CDGT at the 7 nm node for low-power (LP) applications is carried out and extracted electrical characteristics. The proposed CDGT device offers outstanding performance with ON current of 5.5 × 10−4 Amps, an OFF current of 5.9 × 10−12 Amps, and a corresponding switching ratio of 9.3 × 107 at 300 K. Furthermore, this study examined the performance of CDGT on device geometry by scaling of the gate length from 20 nm to 12 nm and Si thickness variation in the range of 5 nm–8 nm. Additionally, the influence of temperature variation is also studied on CDGT and extracted the temperature compensation point (TCP). Moreover, this simulation illustrates the use of CDGT devices for high switching applications with excellent ON current for lower sub 7 nm technology nodes.