Trend of the CMOS process technology for system on a chip

Abstract

The coming 0.13 /spl mu/m technology node will establish the SoC era, in which a chip consists of several systems rather than IPs. But the technology node contains many challenging issues. A new lithography tool with an ArF eximer laser will be required to develop flexible fine patterns. It is predicted that both high speed (high ON current) and low power (low OFF current) would be impossible to achieve on one chip with one process specification. Gate leakage current becomes the biggest challenge against the progress on the road map. Solutions may be diversified at the beginning of the 0.13 /spl mu/m technology node to manage the business chips. High density pattern related ion beam shadowing is another challenge, which will affect the ion implanter specification at this technology node. The precise control of the wafer processing based on the smart integration is the key issue. SOI can provide the solutions to these key challenges.