Double-gate MOSFETs Research Articles

Performance Analysis of Effect of Underlap with Fixed Gate Length: GaN-Based Double Gate MOSFET

Performance Analysis of Effect of Underlap with Fixed Gate Length: GaN-Based Double Gate MOSFET

Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application

In this paper Junctionless Double Gate MOSFET based Efficient Charge Recovery Logic (JL-ECRL) circuits have been driven in sub-threshold regime for the first time in literature to implement the ultra low power systems where the performance is not pivotal issue. Analytical modeling of the power dissipation, delay and the power delay product (PDP) of the sub-threshold JL-Inverter structure have been detailed out. Impact of supply voltage, temperature and the variation of the process parameters like oxide thickness, silicon thickness, doping concentrations have been discussed in depth. Extensive simulations have been done using SILVACO ATLAS to validate analytical data of the power, delay and PDP of the proposed model for different channel length. Based on the analytical and simulated data, optimum conditions have been chosen for the proposed model. It has been observed that the proposed model can perform efficaciously in sub threshold regime without sacrificing noise immunity.

Realization with Fabrication of Double-Gate MOSFET Based Buck Regulator

The traditional buck regulator provides the steady output voltage with high efficiency and low power dissipation. Various parameters of this regulator can be improved by the placement of Double-Gate (DG) MOSFET. The double-gate MOSFET provides twice the drain current flow, which improves the various parameters of buck regulator structure and inevitably increases the device performance and efficiency. In this research work, these parameters have been analyzed with implemented DG MOSFET buck regulator and realized the total losses 42.676 mW and efficiency 74.208%. This research work has designed a DG MOSFET based buck regulator with the specification of input voltage 12 V, output voltage 3.3 V, maximum output current 40 mA, switching frequency 100 kHz, ripple current of 10%, and ripple voltage of 1%.

Influence of SET effects in low-doped double gate MOSFETs

This paper presents study of double gate (DG) MOSFET with the effect of single event transient (SET). Heavy energized ion of 37.2 Linear energy transfer (LET) is strike on source and drain probe of device. Significant amount of Off state drain current (ID) after ion strike is observed. Also, the hole concentration of the device has been increased rapidly.

Compact Noise Modeling Approach in Nano-scaled CSDG MOSFET for RF Switch

The Cylindrical Surrounding Double-Gate (CSDG) MOSFET can be used to design nanotechnology-based switches that can select the signals from various antennas from/to transmitting receiving sections. This model has the advantages of reduced noise for the various switching circuit application of nanotechnology and radio-frequency technology compared to Double-Gate (DG) MOSFET. In this research, a noise model of CSDG MOSFET has been designed and analyzed to apply the nanotechnology regime with the focus on various noises.

Sensitivity of Lightly and Heavily Dopped Cylindrical Surrounding Double-Gate (CSDG) MOSFET to Process Variation

This research work analyzes the sensitivity of Cylindrical Surrounding Double-Gate (CSDG) MOSFET to process variation using the Poisson equation’s analytical solution. This work has been verified with the numerical simulation. Also, the results obtained have been compared with a multi-gate device known as Cylindrical Surrounding Gate (CSG) MOSFETs. The lightly and heavily doped CSDG MOSFETs have been realized. Their immunity to parameter variation (channel length, Silicon thickness, and Random Dopant Fluctuations (RDFs)) has been compared to CSG MOSFET. This research work indicates that lightly doped CSDG MOSFET exhibits the slightest threshold variations than CSG MOSFETs. It confirms that the lightly doped CSDG MOSFET has better immunity to channel variation than CSG MOSFETs. This is due to its structure and inherent internal and external gate geometry, which offers greater control over the channel. However, RDFs become a dominating factor for heavily doped CSG and CSDG MOSFETs, leading to more dispersion in the threshold variations. Therefore, the CSDG MOSFET’s immunity to channel variation becomes deteriorated due to the larger surface-to-volume ratio. At this point, the CSG MOSFET tends to offer better immunity to process variation. Hence, the sensitivity of threshold voltage to parameter variations depends entirely on the RDFs, as the heavily doped devices are aggressively scaled to the nanometer regime.

Capacitive Modeling of Cylindrical Surrounding Double-Gate MOSFETs for Hybrid RF Applications

The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-κ dielectrics. The high-κ dielectric material in place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (CSDG) MOSFET has been realized. The capacitive modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the previous research and tabulated. It has been observed that the transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) values have been raised to 0.0106 S/μm from 0.000645 S/μm with the inclusion of 2D electron gas in the core of CSDG MOSFET. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF applications.

A physical model of cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor

&lt;sec&gt;The cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor (CSDG MOSFET) is formed by adding an internal control gate to the cylindrical surrounding-gate (CSG) MOSFET. The inner gate of CSDG MOSFET acts as a second gate for enhanced charge control. At present, the research of CSDG MOSFET structure is widely concerned. Compared with double-gate MOSFET, triple-gate MOSFET and CSG MOSFET, the CSDG MOSFET provides good controllability of the gate over the channel. Additionally, the device allows for higher volume inversion than CSG MOSFET, which leads to better output characteristics.&lt;/sec&gt;&lt;sec&gt;In order to study the electrical characteristics of CSDG MOSFET, the potential model of CSDG MOSFET is obtained by solving the two-dimensional Poisson equation in cylindrical coordinates. The effects of gate dielectric, channel length and gate dielectric thickness on the surface potential and electric field of CSDG MOSFET are studied. Besides, the drain-source current model of CSDG MOSFET is established by integrating the inverse charge along the channel. The effects of gate dielectric and gate dielectric thickness on the transconductance of CSDG MOSFET are studied. In addition, the effects of the downscaling of device parameters on the transfer characteristics and transconductance of CSDG MOSFET are studied.&lt;/sec&gt;&lt;sec&gt;The electrical characteristics of CSDG MOSFET are analyzed and discussed. The results show that the minimum surface potential along the channel of CSDG MOSFET decreases with the increase of gate dielectric constant of gate dielectric layer. The electric field along the channel and along the radius, drain-source current and transconductance of CSDG MOSFET increase as the gate dielectric constant increases. The threshold voltage of CSDG MOSFET decreases as the gate dielectric constant increases. Moreover, with the downscaling of device parameters, the transfer characteristics and transconductance of CSDG MOSFET decrease. The performance of CSDG MOSFET can be significantly improved by using high-k gate dielectrics. &lt;/sec&gt;

Design and Analysis of InP/InAs/AlGaAs Based Cylindrical Surrounding Double-Gate (CSDG) MOSFETs With La2O3 for 5-nm Technology

Design and Analysis of InP/InAs/AlGaAs Based Cylindrical Surrounding Double-Gate (CSDG) MOSFETs With La₂O₃ for 5-nm Technology

Effect of Temperature on Electrical Behavior of 4H-SiC and 6H-SiC Double-Gate (DG) MOSFETs in 130nm Technology

Effect of Temperature on Electrical Behavior of 4H-SiC and 6H-SiC Double-Gate (DG) MOSFETs in 130nm Technology

Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage ( V TH1 ) could be reduced compared to the external gate ( V TH2 ) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).

Impact of back gate work function for enhancement of analog/RF performance of AJDMDG Stack MOSFET

In this work, the impact of back gate work function on analog/RF performance of Asymmetric Junctionless Dual Material Double Gate MOSFET with high K gate Stack (AJDMDG Stack MOSFET) has been studied. The impact of back gate work function on analog/RF parameters like drain current (ID), transconductance (gm), transconductance generation factor (TGF), intrinsic gain, output resistance (rout), cut-off frequency, maximum frequency of oscillation (fmax) etc. have been studied through TCAD device simulator. The results reveal that an improvement in analog/RF performance has been achieved by choosing a low value work function of the back gate.

Effect of physical parameters on the drain characteristics of Double gate MOSFET incorporating Quantum Mechanical Effects

Scaling of bulk MOSFETs in nanometre regime has several disadvantages. The electrical behaviour of the devices doesn’t show the anticipated characteristics if scaling is done beyond certain point. But in order to have smaller devices with higher density on chips, it is necessary to avoid short channel effects (SCE) which lead to unexpected electrical features. One of the methods to avoid SCE is to have multi-gate architecture of MOSFET. This paper investigates the behaviour of double-gate MOSFETs with respect to the variation of their physical dimensions. The analyses have been done taking into notice the quantum mechanical effects due to dimensions in nanometre scale. The results obtained highlight how subthreshold and above threshold regions are impacted due to the various physical quantities that have been varied.

Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance

This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current of asymmetric junctionless dual material double gate MOSFET with high K gate stack (AJDMDG Stack MOSFET). The electrostatic potential is achieved by solving Poisson’s equation with the help of the parabolic approximation method. Analytical results are verified by using ATLAS TCAD Device simulator. A comparative study of short channel effects (SCEs) of AJDMDG Stack MOSFET and asymmetric junctionless dual material double gate MOSFET with high K gate stack (SJDMDG Stack MOSFET) has been observed in order to show the efficacy of asymmetry condition such as gate oxide asymmetry, gate work function asymmetry etc. for suppressing SCEs. Further, analog/RF performance parameters such as transconductance (gm), output resistance (rout), intrinsic gain, transconductance generation factor (TGF), cut-off frequency (fT), maximum frequency (fmax), gain bandwidth product (GBW) etc. of AJDMDG Stack MOSFET are observed and compared the results with SJDMDG Stack MOSFET structure. Results reveal that AJDMDG Stack MOSFET has better efficacy for RF applications.

Analysis of black phosphorus double gate MOSFET using hybrid method for analogue/RF application

In this work, the authors study the performance of black phosphorus double gate MOSFET (BP-DGMOSFET) within the ballistic limit. A hybrid simulation technique involving both atomistic and technology computer-aided design (TCAD) tool has been used for the first time to simulate the device characteristics. First, the density functional theory has been used to simulate the electrical characteristics of single and fewlayer (five layers) phosphorene (including armchair and zigzag directions). The parameters such as bandgap and effective mass obtained using an atomistic simulator tool are exported into Sentaurus TCAD to simulate the BP-DGMOSFET characteristics. They have used the kinetic velocity model and quantum model to account for the ballistic mobility and quantum effects in the device. The current drain characteristics are calibrated with non-equilibrium Greens function (NEGF) simulation and radio frequency (RF) characteristics with compact model values and found that their results agree with them. Secondly, the other RF figure of merits, such as maximum frequency of oscillation, transconductance, output conductance and stability has also been simulated. It is found that their proposed method shows results comparable to NEGF with reduced computation time and complexity.

The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges

The analog/radiofrequency (RF) performance of a strained-silicon (s-Si) graded-channel dual-material double gate (GC-DMDG) metal–oxide–semiconductor field-effect transistor (MOSFET) with interface charges is investigated by using Sentaurus technology computer-aided design (TCAD) software. The analog/RF figures of merit of the proposed s-Si GC-DMDG MOSFET, including the intrinsic voltage gain, transconductance generation factor, early voltage, unity-current gain frequency ( $$f_{\rm t}$$ ), transconductance–frequency product (TFP), gain–frequency product (GFP), and gain–transconductance–frequency product (GTFP), are evaluated for different values of device parameters such as the strain in the silicon, the interface charge density, and the thicknesses of the oxide and substrate layers. The simulation results exhibit that the proposed s-Si GC-DMDG MOSFET device attains lower values of transconductance and output conductance and a higher value of early voltage compared with the s-Si graded-channel double-gate (GC-DG) MOSFET. Besides, the proposed s-Si GC-DMDG MOSFET device provides better performance in terms of $$f_{\rm t}$$ , TFP, GFP, and GTFP in comparison with the s-Si GC-DG MOSFET in the strong inversion region, and vice versa in the subthreshold region.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub &amp; Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

Analytical modeling of subthreshold current and swing of strained‐Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance

AbstractIn this paper, a two‐dimensional (2‐D) center channel potential based subthreshold current (SC) and subthreshold swing (SS) are developed analytically for strained‐Si (s‐Si) graded‐channel dual‐material double gate (GC‐DMDG) MOSFET with interface charges. The proposed analytical model is extracted by solving 2‐D Poisson equation in s‐Si graded‐channel using appropriate boundary conditions. The analytical 2‐D model includes effects of various MOSFET parameters such as s‐Si channel length, strain in the silicon substrate, and oxide interface charge density with damaged length by extensively analyzing channel potential, SC, and SS. Also, the subthreshold characteristics of the proposed s‐Si GC‐DMDG MOSFET demonstrate superior performance over s‐Si graded channel double gate MOSFET. The numerical results obtained using TCAD of the proposed DG MOSFET are validated with the results attained from proposed analytical model. Moreover, the performance of CMOS inverter using s‐Si GC‐DMDG MOSFET is evaluated for different device parameters. It is investigated that the proposed s‐Si GC‐DMDG MOSFET has better noise margin than s‐Si GC‐DG MOSFET.

Investigation of Single Event Transient Effects in Junctionless Accumulation Mode MOSFET

The Junctionless Accumulation Mode Double Gate MOSFET (JAM DG MOSFET) is a promising novel architecture for future nano-scaled devices because of its outstanding electrical characteristics, e.g., lower subthreshold swing, lower drain induced barrier lowering, i.e., lower short channel effects and higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio. In this paper, a comprehensive analysis of the effects of single-event transient on JAM DG MOSFET has been performed using the sentaurus TCAD simulator. The result shows that the transient drain current peak obtained after the heavy-ion strike for JAM DG MOSFET is small at lower value linear energy transfer (LET) and high for the larger value of LET. Collected charge at different LET values has also been investigated. Moreover, the sensitive region of the device, e.g., source to channel junction, channel, and channel to drain junction has been studied. It has been found that the drain to channel junction is more sensitive to the linear energy than the channel and source to channel junction. The electrical characteristics have also been compared with JL DG MOSFET.

A 2D Analytical Modeling and Simulation of Double Halo Triple Material Surrounding Gate (DH-TMSG) MOSFET

In the nanoscale regime, scaling is the driving force for the miniaturized device applications. Many devices are scaled in size and performance analyses are measured. The scaling of MOSFET leads to the introduction of short channel effects. As the devices are scaled, the magnitude of these short channel effects hinders the performance of the device. In order to minimize these effects, gate engineering and channel engineering are performed. The modification in the gate material is pronounced as gate engineering and the changes in the doping concentration lead to channel engineering. In this paper, a combination of gate and channel engineering is utilized to reduce the short channel effects. A device called double halo triple material surrounding gate(DH-TMSG) MOSFET is introduced for the first time and its 2D analytical model is derived. The performance of the device is analyzed using TCAD ATLAS simulation tool. It has been found from the simulation results that DH-TMSG structure of MOSFET produce the ION current of 10−3A/μm and IOFF current of 10−12A/μm which proves to reduce the leakage current.