Abstract
The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-κ dielectrics. The high-κ dielectric material in place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (CSDG) MOSFET has been realized. The capacitive modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the previous research and tabulated. It has been observed that the transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) values have been raised to 0.0106 S/μm from 0.000645 S/μm with the inclusion of 2D electron gas in the core of CSDG MOSFET. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF applications.
Highlights
Designing an Integrated Circuit (IC), or high-speed semiconductor devices requires a set of protocols or regulations for its series of functionalities-photo-lithography, etching, ion implantation, atomic layer deposition, metal and contact creation, and so on [1]
The current passing through the device is commonly termed as ON-current and the current passing through the insulator or the high-ƙ dielectric material is termed as the leakage current [39]
The center of the cylindrical structure was extracted from the simulation results and the charge density distribution graphs were plotted as in fig. 3(a) double-gate and 3(b) cylindrical surrounding double-gate MOSFET, respectively
Summary
Designing an Integrated Circuit (IC), or high-speed semiconductor devices requires a set of protocols or regulations for its series of functionalities-photo-lithography, etching, ion implantation, atomic layer deposition, metal and contact creation, and so on [1]. The model starts with developing the current equation for the DoubleGate (DG) MOSFET and extends to the nanometer region for the CSDG MOSFET by substituting the equivalent parameters for the cylindrical structure [22] This proposed model has been validated using the results extracted from the electronic device simulator and using predictive model values. The capacitance estimation has been done using the conventional DG MOSFET constraints and expanded to the cylindrical structure with the electrical field model in the oxide layer [26], considering the thickness of the oxide layer [27] It has been maintained less than 10 nm for semiconductor material alloys [28, 29].
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