Double-gate Field-effect Transistor Research Articles

Analytical Modeling of Sensitivity Parameters Influenced by Practically Feasible Arrangement of Bio-Molecules in Dielectric Modulated FET Biosensor

In this paper, analytical modeling of a Dielectric Modulated Double Gate Field Effect Transistor (DM-DGFET) for biosensing application is presented with extensive data analysis. Firstly, the size of the nanogaps and arrangements of biomolecules in those gaps are optimized with respect to the sensitivity of the above sensor. The optimized DM-DGFET is next analyzed on the basis of its modeling and simulation. This paper addresses novel issues arising from arrangements of biomolecules, especially from practical point of view. Effect of probe placement due to steric hindrance and random nature of biomolecules, are also considered. The capacitances associated with the nanogaps occupied by biomolecules, following various arrangements, are modeled. Expressions of the threshold voltage, drain current and its sensitivity in terms of variations are also derived using the capacitance model. A comparative study of the proposed and the existing architectures is made. The influence of process variation on the sensitivity of the sensor is also studied. The results from the proposed analytical model are validated with the simulated data obtained from TCAD device simulator. In conclusion, the proposed DM-DGFET based biosensor architecture will emerge as an optimal model, very useful for the study on this field in future.

DESIGN AND ANALYSIS OF TRI-LAYERED STRAINED CHANNEL DG SHOI FET AT 14 NM

Semiconductor device scaling in deep sub-nm scale strained silicon technology-based double-gate (DG) field effect transistors (FETs) with strained channel developed at 14-nm channel length provides a promising substitute in restricting performance degradation beyond 22 nm technology node. The newly designed double-gate field effect transistor on the insulator is comprised of a three-layer structure s-Si/s-SiGe/s-Si, which is directly deployed in the channel region. But the thickness of channel layers is varied to that in the previously designed 22-nm channel length device, which results in mobility enhancement in the channel region. The linear drive current enhancement is measured analytically with incorporation of the effect of strain on mobility of the charge carrier. Due to additional control with two gates in the device, the charge carrier flows from source to drain, experiencing ballistic transport through the short channel. The DG FET with strained channel designed on a 14-nm technology node provides 53.5% enrichment in drain current to that of a 22-nm channel length with acceptable leakage current.

Positron charge sensing using a double-gated graphene field effect transistor

We utilize a high-mobility double-gated graphene field-effect transistor to measure the accumulated charge created by positron annihilation in its back-gate. The device consists of an exfoliated graphene flake stacked between two hexagonal boron nitride flakes placed on a 1 cm2 substrate of 500 μm thick conducting p-doped Si capped by 285 nm-thick SiO2. The device is placed in close proximity to a 780 kBq 22Na positron source emitting a constant flux of positrons. During the measurement, positrons annihilate within the back-gate, kept floating using a low-capacitance relay. The accumulated positive charge capacitively couples to the graphene device and builds a positive voltage, detectable through a shift in the top-gate dependent graphene resistance characteristic. The shift in the position of the top-gate Dirac peak is then used for extracting the exact voltage buildup and quantitative evaluation of the accumulated charge. Reaching a positron current sensitivity of ∼1.2 fA/Hz, detected over 20min, our results demonstrate the utility of two-dimensional layered materials as probes for charging dynamics of positrons in solids.

Performance improvement in monolayered SnS2 double-gate field-effect transistors via point defect engineering.

Owing to the relatively high carrier mobility and on/off current ratio, monolayered SnS2 has the advantage of suppressing drain-to-source tunneling for short channels, rendering it a promising candidate in field-effect transistor (FET) applications. To extend the scaling limit of the channel length, we propose to rationally modulate the electronic properties of monolayered SnS2 through the customized design of point defects and simulate its performance limit in sub-5 nm double-gate FETs (DGFETs), using density functional theory combined with nonequilibrium Green's function formalism. Among all types of point defects, the Se atom as a substitutional dopant (SeS) can nondegenerately inject electrons into each monolayered (ML) SnS2 2 × 4 × 1 supercell, whereas the Sn vacancy (VSn) defect exhibits an opposite doping effect. By adjusting the lateral Schottky barrier height between electrodes and the channel region, the on-state current (Ion), on/off ratio, delay time, and power-delay product in the formed n-type SeS-doped SnS2 and p-type VSn-doped SnS2 DGFETs with a channel length of 4.5 nm have been remarkably improved, fulfilling the requirements of the International Technology Roadmap for Semiconductors (ITRS) for high-performance applications in the 2028 horizon. Our work unveils the great significance of point defect engineering for applications in ultimately scaled electronics.

Subdomain-based exponential integrators for quantum Liouville-type equations

In order to describe quantum mechanical effects, the use of the von-Neumann equation is apparent. In this work, we present a unified numerical framework so that the von-Neumann equation in center-of-mass coordinates leads to a Quantum Liouville-type equation when choosing a suitable basis. In particular, the proposed approach can be related to the conventional Wigner equation when a plane wave basis is used. The drawback of the numerical methods is the high computational cost. Our presented approach is extended to allow reducing the dimension of the basis, which leads to a computationally efficient and accurate subdomain approach. Not only the steady-state behavior is of interest, but also the dynamic behavior. In order to solve the time-dependent case, suitable approximation methods for the time-dependent exponential integrator are necessary. For this purpose, we also investigate approximations of the exponential integrator based on Faber polynomials and Krylov methods. In order to evaluate and justify our approach, various test cases, including a resonant tunnel diode as well as a double-gate field-effect transistor, are investigated and validated for the stationary and the dynamic device behavior.

Improved performance of sub-10-nm band-to-band tunneling n-i-n graphene nanoribbon field-effect transistors using underlap engineering: A quantum simulation study

In this study, we investigated the effect of underlapping on improving the performance of sub-10-nm band-to-band tunneling (BTBT) double-gate (DG) armchair-edge graphene nanoribbon field-effect transistors (GNRFETs). BTBT was adopted as an operating regime in n-i-n GNRFETs, where p-type doping is not required unlike the conventional p-i-n tunnel FETs. The quantum model employed was based on self-consistently solving the non-equilibrium Green's function and Poisson's equation while considering ballistic transport. Quantum simulation studies were conducted to analyze the impacts of underlapping on direct source-to-drain tunneling and BTBT, which are the dominant quantum mechanical mechanisms in n-i-n GNRFETs that operate in the BTBT regime, where the ambipolar property is induced by thermionic emission. The underlap-induced dilation in the potential barrier dramatically improved the device switching performance according to atomistic simulations. The computational investigation also considered how increasing the underlap length boosted the performance and scaling capacity of the BTBT GNRFETs. Nanodevices with sub-10-nm gate length and an underlap structure exhibited an improved sub-thermionic swing factor, reduced leakage current, and higher current ratios. Despite the slightly reduced on-current due to the underlap-induced dilation in BTBT windows, the recorded improvements in terms of the subthreshold swing, leakage current, and current ratio mean that the sub-10-nm DG BTBT n-i-n GNRFETs with an underlap configuration can potentially be used as steep ultra-scaled transistors for ultra-low power applications.

Electronic Structure and Quantum Transport Properties of 2D SiP: A First-Principles Study

With the rapid evolution of microelectronics, the field of integrated circuits is facing unprecedented challenges. Traditional silicon-based transistors cannot maintain the advantages of high performance during the process of further ultra-scaling due to severe short-channel effects. Two-dimensional (2D) materials are potential channel materials that can replace silicon. Herein, 2D SiP is predicted to have a band gap of 1.49 eV with anisotropic electronic properties by means of first-principles calculations, which is suitable as a channel candidate of transistors. Hence, we investigate the ballistic transport properties of 2D SiP double-gate metal oxide semiconductor field-effect transistors (MOSFETs) by using ab initio quantum transport simulations. Despite anisotropic electronic properties of 2D SiP, the performances of monolayer SiP MOSFETs have weak directional dependence due to high valley degeneracy. The n-MOSFETs with 10-nm gate length can fulfill the high-performance requirements of the International Roadmap for Devices and Systems 2020 Edition (IRDS 2020). However, the p-MOSFETs cannot fulfill the demands of IRDS 2020 because of heavy hole effective masses. Considering the appropriate on-current of 1292 μA/μm for SiP n-MOSFETs, 2D SiP could be utilized as a potential channel material in the next-generation FETs.Graphic abstract

Double-Gate MoS2 Field-Effect Transistors with Full-Range Tunable Threshold Voltage for Multifunctional Logic Circuits.

Multifunctional reconfigurable devices, with higher information capacity, smaller size, and more functions, are urgently needed and draw most attention in frontiers in information technology. 2D semiconductors, ascribing to ultrathin body and easy electrostatic control, show great potential in developing reconfigurable functional units. This work proposes a novel double-gate field-effect transistor architecture with equal top and bottom gate (TG and BG) and realizes flexible optimization of the subthreshold swing (SS) and threshold voltage (VTH ). While the TG and BG are used simultaneously, as a single gate to drive the transistor, ultralow average SS value of 65.5 mV dec-1 can be obtained in a large current range over 104 , enabling the application in high gain inverter. While one gate is used to initialize the channel doping, full logic swing inverter circuit with high noise margin (over 90%) is demonstrated. Such device prototype is further extended for designing reconfigurable logic applications and can be dynamically switched and well maintained between binary and ternary logics. This study provides important concept and device prototype for future multifunctional logic applications.

Channel-hot-carrier degradation in the channel of junctionless transistors: a device- and circuit-level perspective

The performance and reliability enhancement achieved in a conventional double-gate (DG) junctionless field-effect transistor (JLFET) by introducing a vacuum gate dielectric towards the drain terminal and a high- $$\kappa$$ gate dielectric (TiO $$_{2}$$ ) towards the source terminal is investigated. This arrangement of gate dielectrics enables enhanced gate controllability and offers significant protection against channel hot-carrier (CHC) effects at both device and circuit levels. At the device level, the DG-JLFET exhibits a 38% degradation in the drain current due to CHC stress, whereas the vacuum-gate DG-JLFET experiences only one-third of this value. The circuit-level analysis considers three benchmark circuits: ring oscillator (RO), static random-access memory (SRAM) cell, and common-source (CS) amplifier. The oscillating frequency of the RO is improved by 60% with the vacuum gate dielectric, with a 148% lower degradation in performance due to the CHC effect. The proposed approach is thus effective at both levels, not only improving the performance but also significantly enhancing the reliability.

Simulations of monolayer SiC transistors with metallic 1T-phase MoS2 contact for high performance application* *Project supported by the National Natural Science Foundation of China (Grant Nos. 12074046 and 12074115), the Hunan Provincial Natural Science Foundation of China (Grant Nos. 2020JJ4597, 2021JJ40558, and 2021JJ30733), the Scientific Research Fund of Hunan Provincial Education Department, China (Grant Nos. 20K007 and 20C0039), and the

We preform a first-principles study of performance of 5 nm double-gated (DG) Schottky-barrier field effect transistors (SBFETs) based on two-dimensional SiC with monolayer or bilayer metallic 1T-phase MoS2 contacts. Because of the wide bandgap of SiC, the corresponding DG SBFETs can weaken the short channel effect. The calculated transfer characteristics also meet the standard of the high performance transistor summarized by international technology road-map for semiconductors. Moreover, the bilayer metallic 1T-phase MoS2 contacts in three stacking structures all can further raise the ON-state currents of DG SiC SBFETs in varying degrees. The above results are helpful and instructive for design of short channel transistors in the future.

A Highly Scalable Junctionless FET Leaky Integrate-and-Fire Neuron for Spiking Neural Networks

In this article, a highly scalable and CMOS compatible double-gate junctionless field-effect transistor (DG-JLFET)-based leaky integrate-and-fire (LIF) neuron is presented for the sub-20 nm gate length which is the smallest reported until now. Using well-calibrated 2-D TCAD simulations, we demonstrated that DG-JLFET LIF is able to mimic biological neuronal behavior. The DG-JLFET LIF neuron shows a low threshold voltage ( -0.31 V) for firing a spike and requires 1.14 pJ of energy per spike which is ~ 32× less than partially depleted silicon-on-insulator (PD-SOI) MOSFET LIF neuron. The proposed neuron needs only 0.4 V of supply voltage that is ~ 7×, 7.5×, 5×, and 2× lower as compared to its counterpart PD-SOI MOSFET, FinFET, L-shaped bipolar impact ionization MOS (LBIMOS), and Si NIPIN Diode-based LIF neurons, respectively. In addition, at a gate length of 10 nm the DG-JLFET LIF requires 0.07 pJ of energy per spike, which is ~ 500×, ~ 642×, and ~ 86× lower than that of the PD-SOI MOSFET, single MOSFET and Biristor based LIF neurons, respectively. Moreover, the DG-JLFET LIF neuron shows spiking frequency in the range of megahertz, which is ~5 orders high compared to the biological neuron. The absence of metallurgical junctions in DG-JLFET eases the fabrication complexity and cuts down the thermal budget requirement.

Improved logic performance with semiconducting graphene nano mesh double gate field effect transistor

Realisation of field-effect transistors in graphene with an energy gap remains one of the major difficulties for graphene based electronics. One of the solutions to engineer bandgap in graphene is ...

A Physic-Based Explicit Compact Model for Reconfigurable Field-Effect Transistor

In this paper, a compact model for the double-gate Reconfigurable Field-Effect Transistor (RFET) is presented. Firstly, the physics-based surface potential model is derived by solving Poisson's equation at different channel regions. Then an explicit expression of drain current is analytically obtained based on the theory of band-to-band tunneling at the Schottky junction. The proposed model shows excellent agreement with TCAD simulations which have been calibrated with experimental data. Finally, the compactible model is implemented in Verilog-A language without convergence problem, and proven by the RFET-based logic circuit.

Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.

High sensitivity In-Ga-Zn-O nanofiber-based double gate field effect transistors for chemical sensing

Herein, a high sensitivity In-Ga-Zn-O (IGZO) nanofiber channel double gate (DG) field-effect transistor (FET)-based chemical sensor is described. Transparent and flexible IGZO nanofiber channels were fabricated by electrospinning, and IGZO film channels were prepared for comparison via spin coating. We connected a separative extended gate (EG) with a chemical sensing membrane to the fabricated IGZO FETs to test their applicability to pH sensing applications. The effectiveness of the IGZO nanofiber channel was verified by comparing the pH sensitivity and non-ideal effects such as drift and hysteresis voltage with the IGZO film channel. The nanofiber channel showed much higher sensitivity in the dual gate ion-sensitive field-effect transistor (DG ISFET) than the film channel as it has an increased capacitive coupling effect due to an increase in the upper channel surface area and a decreased channel bottom surface area. The sensitivity of the DG ISFET with an IGZO nanofiber channel was 998 mV/pH at room temperature, surpassing the 384 mV/pH of the IGZO film channel, which itself far exceeded the Nernstian limit of 59.16 mV/pH. Furthermore, the nanofiber channel had a lower hysteresis voltage and drift rate compared to its amplified sensitivity, and exhibited a more stable performance than the film channel. Therefore, IGZO nanofiber-based DG FET chemical sensors are expected to be promising for use in transparent and wearable biosensor applications.

Investigation of tied double gate 4H–SiC junctionless FET in 7 nm channel length with a symmetrical dual p+ layer

In this work, we present a novel ultra-thin 4H–SiC junctionless tied double gate field effect (DG-JLFET) transistors with a symmetrical dual p + layer (S-D-P DG-JLFET) and the proposed structure compared with a conventional junctionless tied double gate field effect structure (DG-JLFET). By changing the depletion region in the proposed structure and due to the symmetrical dual p + layer, off-current and drain induced barrier lowering (DIBL) effect is improved but on-current reduces a bit. In our paper, we discuss the work function effect on the off and on-current. Also, the effects of temperature on the electron mobility, the threshold voltage, and changing the lengths of the added p + layers have been investigated. Due to the design complexity of the devices in sub 20-nm, the proper models are considered. The ratio of the I on /I off current of the proposed structure improves significantly versus the conventional double gate junctionless FET. • Improvement in properties of semiconductor physique. • Improvement of control on carrier concentration by gate electrode. • Enhancement of depletion region and better leakage current.

Heavy ion induced single-event-transient effects in nanoscale ferroelectric vertical tunneling transistors by TCAD simulation

Tunnel field-effect transistors (TFETs) are strong candidates for ‘Internet of Things’ electronic devices, due to their ultra-low power consumption. In this work, we propose a novel nanoscale silicon-on-insulator double-gate ferroelectric tunneling field-effect transistor (SOI DG-FeTFET), and single-event-transient (SET) effects are investigated by means of two-dimensional technology computer-aided design simulations. In addition, we perform systematic analysis and comparison with a silicon-on-insulator double-gate ferroelectric field-effect transistor (SOI DG-FeET) . The simulation results show that the peak value of the drain transient current achieved by our DG-FeTFET is up to 2.72 × 10–4 A at 10 MeV·cm2 mg−1, which is much higher than the on-state current (I on) ∼ 7.63 × 10−5 A at V d = 0.5 V. Moreover, our results show that the DG-FeTFET is more susceptible to SET effects than FeFET. The results also show that the bipolar amplification effect can be neglected, and that the drift-diffusion mechanism is dominant in the carrier collection process in the DG-FeTFET. The transient responses of the single event effect are also strongly correlated with the strike location of heavy ions, with the most sensitive part being close to the area where interband tunneling occurs and the electric field is the strongest. These analyses may prove relevant for applications SOI DG-FeTFETs/FeFETs in environments where radiation is present.

Experimental Study on Short-Channel Effects in Double-Gate Silicon Carbide JFETs

Short-channel effects (SCEs) in double-gate silicon carbide junction field-effect transistors (JFETs) fully fabricated by ion implantation are experimentally investigated. The threshold voltage shift, drain-induced barrier lowering, and subthreshold slope degradation are clearly observed in the fabricated p- and n-JFETs. The SCEs are quantitatively evaluated by comparing with the theoretical values obtained by solving a 2-D Poisson equation, which shows good agreement with experiments. The dominant parameter for the SCEs in JFETs is the ratio of the channel length ( ${L}$ ) to the channel thickness ( ${a}$ ), and the device scaling rule to avoid the SCEs is estimated to be ${L}/{a} > {3}$ .

An Analytical Model Including Interface Traps and Temperature Effects in Negative Capacitance Double Gate Field Effect Transistor

In this paper, an analytical model for negative capacitance double gate field effect transistor (NC-DG-FET) is proposed. This model includes interface traps and temperature effects, which are ignored in previous investigations. In addition, the impacts of the ferroelectric thickness tFE, the interface trap density Dit and temperature T on the device performance are comprehensively discussed. The results indicate that, the minimum subthreshold swing is about 14 mV/decade with tFE = 75 nm, Dit = 5 × 1010 cm− 2/eV, T = 300 K. As Dit increases, the flat band voltage is decreased, which results in a gain peaking at a lower gate voltage, and a steeper subthreshold slope. When the temperature is raised from 300 K to 380 K, the NC effect is gradually weakened, resulting in a decrease in gain, and a smoothing of the subthreshold slope. We have verified our model by comparing it with experimental data and numerical simulation.

Double-Gate MoS2 Field-Effect Transistor with a Multilayer Graphene Floating Gate: A Versatile Device for Logic, Memory, and Synaptic Applications.

2D materials with low-temperature processing hold promise for electronic devices that augment conventional silicon technology. To meet this promise, devices should have capabilities not easily achieved with silicon technology, including planar fully-depleted silicon-on-insulator with substrate body-bias, or vertical finFETs with no body-bias capability. In this work, we fabricate and characterize a device [a double-gate MoS2 field-effect transistor (FET) with hexagonal boron nitride (h-BN) gate dielectrics and a multi-layer graphene floating gate (FG)] in multiple operating conditions to demonstrate logic, memory, and synaptic applications; a range of h-BN thicknesses is investigated for charge retention in the FG. In particular, we demonstrate this device as a (i) logic FET with adjustable VT by charges stored in the FG, (ii) digital flash memory with lower pass-through voltage to enable improved reliability, and (iii) synaptic device with decoupling of tunneling and gate dielectrics to achieve a symmetric program/erase conductance change. Overall, this versatile device, compatible to back-end-of-line integration, could readily augment silicon technology.