Double-gate Field-effect Transistor Research Articles

Analytical modeling of uniaxial strain effects on the performance of double-gate graphene nanoribbon field-effect transistors

The effects of uniaxial tensile strain on the ultimate performance of a dual-gated graphene nanoribbon field-effect transistor (GNR-FET) are studied using a fully analytical model based on effective mass approximation and semiclassical ballistic transport. The model incorporates the effects of edge bond relaxation and third nearest neighbor (3NN) interaction. To calculate the performance metrics of GNR-FETs, analytical expressions are used for the charge density, quantum capacitance, and drain current as functions of both gate and drain voltages. It is found that the current under a fixed bias can change several times with applied uniaxial strain and these changes are strongly related to strain-induced changes in both band gap and effective mass of the GNR. Intrinsic switching delay time, cutoff frequency, and Ion/Ioff ratio are also calculated for various uniaxial strain values. The results indicate that the variation in both cutoff frequency and Ion/Ioff ratio versus applied tensile strain inversely corresponds to that of the band gap and effective mass. Although a significant high frequency and switching performance can be achieved by uniaxial strain engineering, tradeoff issues should be carefully considered.

Toward Low-Power Electronics: Tunneling Phenomena in Transition Metal Dichalcogenides

In this article, we explore, experimentally, the impact of band-to-band tunneling on the electronic transport of double-gated WSe2 field-effect transistors (FETs) and Schottky barrier tunneling of holes in back-gated MoS2 FETs. We show that by scaling the flake thickness and the thickness of the gate oxide, the tunneling current can be increased by several orders of magnitude. We also perform numerical calculations based on Landauer formalism and WKB approximation to explain our experimental findings. Based on our simple model, we discuss the impact of band gap and effective mass on the band-to-band tunneling current and evaluate the performance limits for a set of dichalcogenides in the context of tunneling transistors for low-power applications. Our findings suggest that WTe2 is an excellent choice for tunneling field-effect transistors.

Simplified drain current model for pinch‐off double gate junctionless transistor

A simplified analytical drain current model for the long-channel pinch-off junctionless (JL) double-gate field effect transistor (DGFET) is proposed. The drain current is generally expressed in terms of the mobile charge density and it has been expressed in terms of the pinch-off voltage and the gate capacitance. The proposed model is validated against TCAD simulation results, and is able to predict the behaviour of the JL DGFET for different bias conditions and device dimensions, accurately. The transconductance and the transconductance-to-drain-current ratio are important parameters for analogue circuits, and have been calculated and exhibit good agreement with the TCAD results.

An Open-Source Multiscale Framework for the Simulation of Nanoscale Devices

We present a general simulation framework for assessing the performance of nanoscale devices that combines several powerful and widely used open-source codes, and based on minimal but chemically accurate tight-binding Hamiltonians obtained from density-functional theory calculations and using maximally localized Wannier functions to represent the electronic state. Transport properties are then computed within the nonequilibrium Green's function formalism. We illustrate the capabilities of this framework applying it to a transistor with generic gate geometries, i.e., a double-gate nanoscale field-effect transistor where the channel is formed by graphene nanoribbons terminated with hydrogen, fluorine, and OH groups.

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar transistors, are devices whose polarity is online reconfigurable by changing the second gate bias. In this brief, we exploit the online control of ambipolar device polarity to achieve intrinsically power-gated DCVSL circuits bypassing the use of series sleep transistors. We perform circuit-level simulations and comparisons at 22-nm technology node, considering silicon nanowire -based DG controllable-polarity FETs. Experimental results show that ambipolar DCVSL circuits power gated by the proposed technique have on average 6× smaller standby power with only 1.1× timing penalty with respect to their non-power-gated versions. As compared with unipolar FinFET-based realizations, our proposal is capable to reduce up to 1.9× the standby power consumption of a low-standby-power process and, at the same time, increase up to 10% the performance of a high-performance process.

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.

Explicit drain current model of junctionless double-gate field-effect transistors

This paper presents an explicit drain current model for the junctionless double-gate metal–oxide–semiconductor field-effect transistor. Analytical relationships for the channel charge densities and for the drain current are derived as explicit functions of applied terminal voltages and structural parameters. The model is validated with 2D numerical simulations for a large range of channel thicknesses and is found to be very accurate for doping densities exceeding 1018cm−3, which are actually used for such devices.

A first-principles study on the effect of biaxial strain on the ultimate performance of monolayer MoS2-based double gate field effect transistor

In this work, the effect of biaxial strain on the electronic band structure of monolayers of MoS2 is investigated. The effective mass of carriers under different strain values is extracted and the achieved results are discussed. For the first time, we have assessed the effect of biaxial strain on the ultimate performance of MoS2-based double gate field effect transistors (DGFETs). The results indicate that by strain engineering, a significant performance improvement of MoS2-based DGFETs can be achieved.

Suppression of threshold voltage variability of double-gate fin field-effect transistors using amorphous metal gate with uniform work function

An amorphous TaSiN metal gate (MG) is introduced into double-gate fin field-effect transistors (FinFETs) to suppress work function variation (WFV) of the MG, which is a dominant source of threshold voltage (Vt) variability for MG FinFETs. Comparing with a poly-crystalline TiN gate, the TaSiN gate reduces Vt variation dramatically and thus records the smallest AVt value of 1.34 mV μm reported so far for the MG-FinFETs. By decomposing the variation source due to interface trap density, the WFV suppression using the amorphous MG is confirmed to be effective to achieve the well-suppressed variability of the MG-FinFETs.

Analytical models for the electric potential, threshold voltage and drain current of long-channel junctionless double-gate transistors

Analytical models for the electric potential, threshold voltage and drain current of long-channel junctionless (JL) double-gate (DG) field-effect transistors (FET) are presented. A regional method is used to solve the Poisson equation under different gate biases, and the electric potential is obtained. With the potential model, an analytical expression for the threshold voltage is achieved. An expression for the drain current is derived from the potential model. The analytical results are compared with simulations, and excellent agreements are observed. The models accurately describe the characteristics of JLDG FETs, and they are very helpful for the design and optimization of devices.

Semianalytical Model of the Subthreshold Current in Short-Channel Junctionless Symmetric Double-Gate Field-Effect Transistors

A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations.

Simulation study on short channel double-gate junctionless field-effect transistors

We study the characteristics of short channel double-gate (DG) junctionless (JL) FETs by device simulation. Output I–V characteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed. Distributions of electron concentration, electric field and potential in the body channel region are also analyzed. Comparisons with conventional inversion-mode (IM) FETs, which can demonstrate the advantages of JL FETs, have also been performed.

A pH sensor with a double-gate silicon nanowire field-effect transistor

A pH sensor composed of a double-gate silicon nanowire field-effect transistor (DG Si-NW FET) is demonstrated. The proposed DG Si-NW FET allows the independent addressing of the gate voltage and hence improves the sensing capability through an application of asymmetric gate voltage between the two gates. One gate is a driving gate which controls the current flow, and the other is a supporting gate which amplifies the shift of the threshold voltage, which is a sensing metric, and which arises from changes in the pH. The pH signal is also amplified through modulation of the gate oxide thickness.

Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits

Power consumption has become a very important consideration during integrated circuit (IC) design and test. During test, it can far exceed the values reached during normal operation and, thus, lead to temperatures above the allowed threshold. Without appropriate temperature reduction, permanent damage may be caused to the IC or invalid test results may be obtained. FinFET is a double-gate field-effect transistor (DG-FET) that was introduced commercially in 2012. Due to the vertical nature of FinFETs and, hence, weaker ability to dissipate heat, this problem is likely to get worse for FinFET circuits. Another technology rapidly gaining popularity is 3D IC integration. Unfortunately, the compact nature of a multidie 3D IC is likely to aggravate the temperature-during-test problem even further. Hence, before temperature-aware test methodologies can be developed, it is important to thermally analyze both FinFET and 3D circuits under test. In this article, we present a methodology for thermal characterization of various test techniques, such as scan and built-in self-test (BIST), for FinFET and 3D ICs. FinFET thermal characterization makes use of a FinFET standard cell library that is characterized with the help of the University of Florida double-gate (UFDG) SPICE model. Thermal profiles for circuits under test are produced by ISAC2 from University of Colorado for FinFET circuits and HotSpot from University of Virginia for 3D ICs. Experimental results indicate that high temperatures result under BIST and much less often under scan, and that both power consumption and test application time should be reduced to lower the temperature of circuits under test, just reducing the power consumption is not enough.

Design and Analysis of Johnson Counter Using Finfet Technology

Conventional CMOS technology's performance deteriorates due to increased short channel effects. Double-gate (DG) FinFETs has better short channel effects performance compared to the conventional CMOS and stimulates technology scaling. The main drawback of using CMOS transistors are high power consumption and high leakage current. Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano- scale circuits.FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate field effect transistors because it has two gates that can be controlled independently. Usually, the second gate of FinFET transistors is used to dynamically control the threshold voltage of the first gate in order to improve the performance and reduce leakage power. In this paper, we proposes a synchronous johnson counter by using FinFET Technology.FinFET logic implementation has significant advantages over static CMOS logic in terms of power consumption. The proposed counter was fabricated in 16nm FinFET technology in HSPICE.

A transistor-based biosensor for the extraction of physical properties from biomolecules

An analytical technique is proposed that uses an asymmetric double-gate field-effect transistor (FET) structure to characterize the electrical properties of biomolecules, including their permittivity and charge density. Using a simple measurement with the proposed FET structure, we are able to extract the physical properties (i.e., permittivity and charge density) of biomolecules. A reliable analytical tool for the characterization of biomolecules can be provided by the proposed FET structure without a complex measurement system. It is expected that the proposed method will be expanded into a universal analysis technique for the electrical evaluation of biomolecules in applications beyond biosensing.

A New Approach to the Characteristics and Short-Channel Effects of Double-Gate Carbon Nanotube Field-Effect Transistors using MATLAB: A Numerical Study

In this paper, first, the impact of different gate arrangements on the short-channel effects of carbon nanotube field-effect transistors with doped source and drain with the self-consistent solution of the three-dimensional Poisson equation and the Schr¨odinger equation with open boundary conditions, within the non-equilibrium Green function, is investigated. The results indicate that the double-gate structure possesses a quasi-ideal subthreshold oscillation and an acceptable decrease in the drain induced barrier even for a relatively thick gate oxide (5 nm). Afterward, the electrical characteristics of the double-gate carbon nanotube field-effect transistors (DG-CNTFET) are investigated. The results demonstrate that an increase in diameter and density of the nanotubes in the DG-CNTFET increases the on-state current. Also, as the drain voltage increases, the off-state current of the DG-CNTFET decreases. In addition, regarding the negative gate voltages, for a high drain voltage, increasing in the drain current due to band-to-band tunnelling requires a larger negative gate voltage, and for a low drain voltage, resonant states appear

Tunable contact resistance in double-gate organic field-effect transistors

A study of the contact resistance (Rsd) in pentacene-based double-gate transistors is presented. In top-contact transistors, as the negative bias of the additional top-gate bias is increased, Rsd decreases by over five orders of magnitude for small bottom-gate voltages. In bottom-contact transistors, Rsd is reduced by about ten times for all bias values, implying improved charge transport in all operating regimes. The different tunability of Rsd in top/bottom-contact transistors is attributed to different charge injection modulation by the coplanar/staggered top gate. Therefore, double-gate architecture offers a novel and effective approach to limit Rsd and its relevant impacts on organic transistor.

Use of negative capacitance to simulate the electrical characteristics in double-gate ferroelectric field-effect transistors

The surface potential and drain current of double-gate metal-ferroelectric-insulator-semiconductor (MFIS) field-effect transistor were investigated by using the ferroelectric negative capacitance. The derived results demonstrated that the up-converted semiconductor surface potential and low subthreshold swing S = 34 (<60 mV/dec) can be realized with appropriate thicknesses of ferroelectric thin film and insulator layer at room temperature. What's more, a reduction gate voltage about 260 mV can be reached if the ON-state current is fixed to 600 μA/μm. It is expected that the derived results can offer useful guidelines for the application of low power dissipation in ongoing scaling of FETs.

Physical insights on comparable electron transport in (100) and (110) double-gate fin field-effect transistors

We have investigated the physical mechanisms that result in comparable electron mobility measured from (100) and (110) sidewall double-gate fin field-effect transistors (FinFETs). Using a self-consistent Schrodinger-Poisson simulator coupled with a sp3d5s* tight-binding bandstructure, we have shown that the (100)/〈100〉 and (110)/〈110〉 average conductivity effective mass values are similar. This is explained by the much heavier non-parabolic confinement mass for Δ2 valley of (110) FinFETs, which leads to lower Δ2 energy than Δ4. Thus, for both (100) and (110), the majority of electrons occupy the Δ2 valley with 0.19m0 conductivity effective mass, resulting in comparable electron mobility.