Experimental Study on Short-Channel Effects in Double-Gate Silicon Carbide JFETs

Abstract

Short-channel effects (SCEs) in double-gate silicon carbide junction field-effect transistors (JFETs) fully fabricated by ion implantation are experimentally investigated. The threshold voltage shift, drain-induced barrier lowering, and subthreshold slope degradation are clearly observed in the fabricated p- and n-JFETs. The SCEs are quantitatively evaluated by comparing with the theoretical values obtained by solving a 2-D Poisson equation, which shows good agreement with experiments. The dominant parameter for the SCEs in JFETs is the ratio of the channel length ( ${L}$ ) to the channel thickness ( ${a}$ ), and the device scaling rule to avoid the SCEs is estimated to be ${L}/{a} > {3}$ .