DESIGN AND ANALYSIS OF TRI-LAYERED STRAINED CHANNEL DG SHOI FET AT 14 NM

Abstract

Semiconductor device scaling in deep sub-nm scale strained silicon technology-based double-gate (DG) field effect transistors (FETs) with strained channel developed at 14-nm channel length provides a promising substitute in restricting performance degradation beyond 22 nm technology node. The newly designed double-gate field effect transistor on the insulator is comprised of a three-layer structure s-Si/s-SiGe/s-Si, which is directly deployed in the channel region. But the thickness of channel layers is varied to that in the previously designed 22-nm channel length device, which results in mobility enhancement in the channel region. The linear drive current enhancement is measured analytically with incorporation of the effect of strain on mobility of the charge carrier. Due to additional control with two gates in the device, the charge carrier flows from source to drain, experiencing ballistic transport through the short channel. The DG FET with strained channel designed on a 14-nm technology node provides 53.5% enrichment in drain current to that of a 22-nm channel length with acceptable leakage current.