An Analytical Model Including Interface Traps and Temperature Effects in Negative Capacitance Double Gate Field Effect Transistor

Abstract

In this paper, an analytical model for negative capacitance double gate field effect transistor (NC-DG-FET) is proposed. This model includes interface traps and temperature effects, which are ignored in previous investigations. In addition, the impacts of the ferroelectric thickness tFE, the interface trap density Dit and temperature T on the device performance are comprehensively discussed. The results indicate that, the minimum subthreshold swing is about 14 mV/decade with tFE = 75 nm, Dit = 5 × 1010 cm− 2/eV, T = 300 K. As Dit increases, the flat band voltage is decreased, which results in a gain peaking at a lower gate voltage, and a steeper subthreshold slope. When the temperature is raised from 300 K to 380 K, the NC effect is gradually weakened, resulting in a decrease in gain, and a smoothing of the subthreshold slope. We have verified our model by comparing it with experimental data and numerical simulation.