Double-edge Triggered Flip-flop Research Articles

Fault modeling for external energy or internal cell defect in quantum dot cellular automata

Nanotechnology has made the circuits more susceptible to errors. It takes a lot of space and power to make sequential reversible circuits testable using one of the conventional methods (such as cascading gates with the original circuit). I suggest a superior testing strategy for sequential circuits based on conservative logic. The primary goal of this effort is to create a testable sequential circuit that is compact in terms of circuit area and other cost parameters. My method does not require changing the original circuit. So, incorporating testable features using the proposed method does not affect the complexity of the overall circuit. In this work, stuck-at-fault modeling for external unwanted energy or internal cell defect in low-power molecular QCA is also derived. The reversible double-edge triggered (DET) flip-flop is tested using the suggested approach. The proposed methodology can still be applied to achieve 100% fault coverage for unidirectional stuck-at-fault in quantum cellular automata (QCA) designs. The design is assigned into practice using a layered technique since it is more reliable and economical.

Design of double edge-triggered flip-flop with low power consumption

As is well known, the power consumption of integrated circuits (ICs) is considered one of the most important problems for high-performance chips. Accordingly, for any chip design, power consumption has to be taken into account very seriously. In this paper, a low-power double edge-triggered (DET) D-type flip-flop circuit is proposed. This allows the frequency of the clock signal to be reduced by half, reducing system complexity and reducing power consumption. In addition, the proposed flip-flop can be implemented with fewer transistors than any previous circuit, and hence requires a small area. Simulation results indicated that the proposed circuit is capable of significant delay and power saving.

Design and Speed Analysis of Low Power Single and Double Edge Triggered Flip Flop with Pulse Signal Feed-Through Scheme

Flip flop is a fundamental electrical design component. Most electrical designs incorporate memory and their corresponding designs. The consumer electronics or end users need mobility and extended battery backup to enhance design performance. The focus on any parameter in the system is to maximize the performance of the design. Here the task is to reduce the energy use of flip flop. Due to the increased frequency clock delivered to the networks within the design, the edge or level triggered by a flip flop will contribute to power consumption. Due to the short circuit power consumption between ground and Vdd, the static design of the flip flop will increase power consumption. The flip flop is dynamically designed and implemented, leading to higher leakage power. Dynamic clock implementation helps for short-circuit power avoidance. It also provides greater download channel to the ground from output. The clocking system also demands more power. With the TSPC technology and output feedback, the suggested mechanic will increase the performance of the flip flop and establish the Pull-up network. The PMOS that contains the output node X value. The use of an additional NMOS transistor to draw the output value down to the ground, regardless of the input, so that the input runs on the discharge path that improves power, however the pulsed clock which has a smaller width than normal clock as well about 15% high.

Anti-interference low-power double-edge triggered flip-flop based on C-elements

When the input signal has been interfered and glitches occur, the power consumption of Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce the power consumption, this paper presents an anti-interference low-power DETFF based on C-elements. The improved C-element is used in this DETFF, which effectively blocks the glitches in the input signal, prevents redundant transitions inside the DETFF, and reduces the charge and discharge frequencies of the transistor. The C-element has also added pull-up and pull-down paths, reducing its latency. Compared with other existing DETFFs, the DETFF proposed in this paper only flips once on the clock edge, which greatly reduces the redundant transitions caused by glitches and effectively reduces power consumption. This paper uses HSPICE to simulate the proposed DETFF and other 10 DETFFs. The findings show that compared with the other 10 types of DETFFs, the proposed DETFF has achieved large performance indexes in the total power consumption, total power consumption with glitches, delays, and power delay product. A detailed analysis of variance indicates that the proposed DETFF features less sensitivity to process, voltage, temperature, and Negative Bias Temperature Instability (NBTI)-induced aging variations.

Design of double edge-triggered flip-flop for low-power educational environment

Power consumption plays a significant role in any integrated circuit. In this study, an explicit type pulse trigger flip-flop is implemented using the CMOS 90 nm technology. For low-power dissipation, 1 V supply will optimize the size of gate terminal. This explicit type flip-flop uses an explicit source for pulse generation, that is, the double edge-triggered pulse generator, which requires half of clock frequency compared to the single edge-triggered pulse generator. The proposed new double edge-triggered pulse generator uses the pulse generation logic, which is used to share many numbers of flip-flop results at low power. In this article, circuits with low power, low heat generation, and increased durability are achieved.

Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications

The logic construction of a double-edge-triggered (DET) flipflop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flip flops. By simulating and comparing the proposed DET flip-flop with the other designs present, it is shown that the proposed DET flip-flop reduces power dissipation while keeping the same date rate and can be used for high speed applications.

A general structure of all-edges-triggered flip-flop based on multivalued clock

According to the principle of the binary DETFF (double-edge-triggered flip-flop) based on binary clock, and the switching rule of the logic values of multivalued clock, this article proposes a general structure of AETFF (all-edges-triggered flip-flop) based on multivalued clock that makes the most of the large information-carrying capacity of multivalued signal. Binary or multivalued AETFFs based on arbitrary radices clocks can be designed by referring to the general structure, and are sensitive to every edge of multivalued clocks with a simple structure, high efficiency and low power, which can be implemented not only by CMOS technology, but also by next generation of devices with multiple states. At last, CMOS quaternary AETFF based on quaternary clock was implemented based on the general structure and the transmission function theory, and simulated in HSPICE, its ideal logic functionality being shown.

Design of Testable Reversible Sequential Circuits

In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1's, and all 0's. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible design of the DET flip-flop is proposed for the first time in the literature. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum-dot cellular automata (QCA) layout of the Fredkin gate. We are also presenting a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area.

Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Double-edge triggered flip-flops offer a solution to clock power reduction by lowering the clock frequency and maintaining the same data rate. A compact 9-transistor double-edge triggered flip-flop for reducing flip-flop power is proposed. A combination of a selective swing-based partial transmission gate (TG) approach and multi-Vt transistors is used to make it area and power-efficient. The selective swing-based transmission gate approach reduces the transistor count, and the selective use of low-Vt transistors overcomes the effect of any intermediate low swing voltage levels in the circuit due to a partial TG approach. Low transistor count reduces capacitive load of the dynamic power component, and selective use of low-Vt transistors improves circuit performance as well as reduces power-delay product. The proposed circuit is implemented in the Samsung 130nm 1P6M Multi-Vt CMOS process technology and simulated for various PVT conditions. Results show that the power consumption of the circuit is reduced by 9.58% and energy reduced by 14.2% with a 5.12% improvement in speed for a slow process when compared to the previous techniques.

Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits

Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented.

Energy-Efficient Double-Edge Triggered Flip-Flop

This paper presents a novel design for a double-edge triggered flip-flop (DETFF). A detailed analysis of the transistors used in the DETFF is carried out to determine the critical path. Therefore, the proposed DETFF employs low-V th transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-V th transistors can be resolved simultaneously. Therefore, the proposed DETFF fully utilizes the multi-V th scheme provided by advanced CMOS processes without suffering from a large area penalty, slow clock frequency, and poor noise immunity. The proposed design is implemented using a typical 0.18-μm 1P6M CMOS process. The measurement results reveal that the proposed DETFF reduce the power-delay product by at lease 25% (i.e., dissipated energy).

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively

A low-swing clock double-edge triggered flip-flop

A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V/sub t/ transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network.

A static differential double edge-triggered flip–flop based on clock racing

In this paper, a double edge-triggered (DET) flip–flop is proposed, suitable for high-performance and low-power applications. The presented flip–flop has differential structure and provides static operation. The double edge triggering operation is achieved, by generating a narrow pulse immediately after each clocking edge, which is used to set the flip–flop in the transparent phase. The narrow pulse generation technique is based on a clock racing methodology. Compared to existing DET flip–flops, the proposed DET flip–flop results in significant delay and power gains, but keeps the total transistor count low. By applying the narrow pulse to more than one similar adjacent DET flip–flops, we can further reduce the power and the transistor count.

High performance double edge-triggered flip-flop using a merged feedback technique

Double edge-triggered flip-flops (DETFFs) use both edges of the clock to latch data and hence can lead to significant power saving over single edge-triggered flip-flops for a fixed data rate. However, existing DETFF implementations suffer from the problems of charge sharing, charge coupling, incomplete voltage swing, poor voltage scaling properties and excessive power dissipation. A new DETFF is proposed, which does not suffer from any of these problems and can operate at a clock speed which is 1.33 times that of the best double edge-triggered flip-flop available today. With reduced supply voltages, this flip-flop results in lower power dissipation and maintains a comparable performance to, if not better than, existing DETFFs.

Low power double edge-triggered flip-flop using one latch

Low power double edge-triggered flip-flop using one latch A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops.

Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings"

For original paper see J. Yuan and C. Svensson, ibid., vol.32, pp.62-69 (1997). In a recent paper, Yuan and Svensson propose various single-clock differential flip-flops; however, those using a dynamic slave are unsafe in the presence of input glitches. Further, a double-edge triggered flip-flop is developed from one of the semistatic versions.

Low-power double-edge triggered flipflop

Low-power double-edge triggered flipflops are presented using weak feedback transistors which allow purely n-type transmission gates, but without static-power consumption. The switching capacitance of the weak transistors is minimised by using permanently ON transistors in series as resistive devices. Both static and semi-static circuits are presented.