Abstract
Multithreshold MOS Current Mode Logic (MCML) implementation of asynchronous pipeline circuits, namely, a C-element and a double-edge triggered flip-flop is proposed. These circuits use multiple-threshold MOS transistors for reducing power consumption. The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits. The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones. To demonstrate the functionality of the proposed circuits, an asynchronous FIFO has also been implemented.
Highlights
Digital VLSI circuits can be broadly classified into synchronous and asynchronous circuits
MT-MOS Current Mode Logic (MCML) circuits can be used in low-power applications as they can operate at low supply voltage than the conventional one
The simulation results for an asynchronous FIFO are presented
Summary
Digital VLSI circuits can be broadly classified into synchronous and asynchronous circuits. MOS Current Mode Logic (MCML) is found to be an alternative to the CMOS asynchronous circuits in the literature [2,3,4,5]. The circuit has static power consumption given as the product of the supply voltage and the bias current. The power consumption can be lowered by either reducing the bias current or the supply voltage. MT-MCML technique has been applied to implement low-power multithreshold MCML asynchronous pipeline circuits.
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