Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Abstract

Double-edge triggered flip-flops offer a solution to clock power reduction by lowering the clock frequency and maintaining the same data rate. A compact 9-transistor double-edge triggered flip-flop for reducing flip-flop power is proposed. A combination of a selective swing-based partial transmission gate (TG) approach and multi-Vt transistors is used to make it area and power-efficient. The selective swing-based transmission gate approach reduces the transistor count, and the selective use of low-Vt transistors overcomes the effect of any intermediate low swing voltage levels in the circuit due to a partial TG approach. Low transistor count reduces capacitive load of the dynamic power component, and selective use of low-Vt transistors improves circuit performance as well as reduces power-delay product. The proposed circuit is implemented in the Samsung 130nm 1P6M Multi-Vt CMOS process technology and simulated for various PVT conditions. Results show that the power consumption of the circuit is reduced by 9.58% and energy reduced by 14.2% with a 5.12% improvement in speed for a slow process when compared to the previous techniques.