A static differential double edge-triggered flip–flop based on clock racing

Abstract

In this paper, a double edge-triggered (DET) flip–flop is proposed, suitable for high-performance and low-power applications. The presented flip–flop has differential structure and provides static operation. The double edge triggering operation is achieved, by generating a narrow pulse immediately after each clocking edge, which is used to set the flip–flop in the transparent phase. The narrow pulse generation technique is based on a clock racing methodology. Compared to existing DET flip–flops, the proposed DET flip–flop results in significant delay and power gains, but keeps the total transistor count low. By applying the narrow pulse to more than one similar adjacent DET flip–flops, we can further reduce the power and the transistor count.