Low power double edge-triggeredflip-flop using one latch

Abstract

Low power double edge-triggered flip-flop using one latch A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops.