Abstract
As is well known, the power consumption of integrated circuits (ICs) is considered one of the most important problems for high-performance chips. Accordingly, for any chip design, power consumption has to be taken into account very seriously. In this paper, a low-power double edge-triggered (DET) D-type flip-flop circuit is proposed. This allows the frequency of the clock signal to be reduced by half, reducing system complexity and reducing power consumption. In addition, the proposed flip-flop can be implemented with fewer transistors than any previous circuit, and hence requires a small area. Simulation results indicated that the proposed circuit is capable of significant delay and power saving.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of Scholarly Research in Engineering and Technology
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
