A Low Power and Small Area FFT Processor for OFDM Demodulator

Abstract

The FFT (fast Fourier transform) processor is the most speed and power consumption critical part in the orthogonal frequency division multiplexing (OFDM) communication system. In this paper, a low power consumption and small area FFT processor architecture suitable for OFDM demodulators is proposed. In order to meet the requirements of high-speed data throughput and low power and small area consumption, distributed memory architecture is developed to meet the requirement of non-stopping and high-speed data throughput. One clock-cycle mixed radix-2/4 butterfly architecture is proposed for OFDM. Meanwhile, due to the two radix-2 and radix-4 butterflies share in the two complex multipliers, the FFT processor with the proposed radix-2/4 butterfly can make the 64% power consumption reduction and the 35% gate count reduction, respectively. Performance analysis shows that the proposed FFT architecture can meet the requirement of OFDM demodulators in DVB-T and other high speed wireless applications.