A reconfigurable ASIP for high-throughput and flexible FFT processing in SDR environment

Abstract

ABSTRACT This paper presents a high-throughput and reconfigurable processor for fast Fourier transformation (FFT) processing based on SDR methodology. It adopts application specific instruction-set (ASIP) and single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. Moreover, a novel 3-dimension multi-bank memory is proposed for parallel conflict-free accesses. The overall throughput and power-efficiency are greatly enhanced by parallel and streamline processing. A test chip supporting 64~2048-point FFT is setup for experiment. Logic synthesis reveals a maximum clock frequency of 500MHz and an area of 0.49 mm 2 for the processor's logic using a low power 45-nm technology, and the dynamic power estimation is about 96.6mW. Compared with previous works, our FFT ASIP achieves a higher energy-efficiency with relative low area cost. Keywords: FFT, SDR, SIMD processor. 1. INTRODUCTION Nowadays, digital communication is becoming more and more diversified and complex. Flexibility becomes a dominant aspect for the transceiver. Software defined radio (SDR) is considered as a promising methodology which provides a flexible solution and supports multiple standards fully implemented or controlled by software on a single platform. Foremost, it shorts the development cy cle and alleviates time -to-market pressure. This paper focuses on the FFT processing in mobile and wireless communication system in the context of SDR. FFT processing is one of the most critical components in the Orthogonal Frequency-Division Multiplexing (OFDM)-based systems. It directly affects the throughpu t of system and accuracy of the channel estimation [1]. As the data transmission rate of OFDM systems increases, generating high data rate OFDM symbols requires very high speed FFT processor. In addition to the high throughput requirement, another key feature of the current 3G and 4G wireless systems is that the processor should be easily reprogrammed or reconfigured to support various standards and operating modes. This imposes a requirement of high flexibility on FFT processing . Hence, efficiently implemen ting the FFT with low power and appropriate flexibility is very important , particularly for the portable devices. Traditional FFT coprocessors are mainly divided into pipeline architecture [2] and cache/memory architecture [3]. All of them use multiple butterfly computation units or extra memory storage resource to support limited flexibility, which cost a lot both in power and area consumption. A general purpose digital signal processor (DSP) has high flexibility and low development cost, but consumes much power and only achieves medium performance. Thus it is not suitable for handsets. Recently, platforms for SDR [5, 6] are proposed for wireless baseband signal processing. They feature multiprocessor systems with single-instruction multiple-data (SIMD) vector processing engines to exploit the parallelism of different algorithms. In case of signal processing on-demand architecture (SODA), which consists of a simple RISC processor and four uniform vector DSP cores with app lication specific instructions. It minimizes the usage of coprocessors and implements most computational intensive baseband algorithms on the vector DSP cores, which reduces the total chip area, data storage and date move ment between coprocessors and the main processor. This paper proposes a reconfigurable FFT ASIP exploiting high computati onal parallelism and low memory access based on a very long instruction word (VLIW) and SIMD ar chitecture. We enhance the power efficiency by extending our previous work in [6] with wider SIMD lanes, optimized vector function units and a more efficient memory structure. The proposed architecture provides a high flexibility and scalability for any size of FFT algorithms.