Abstract
In modern electronics, the continuous growth of wearable and portable devices like mobile phones, laptops and smart watches demands low-power consumption. Since flip-flop is a basic storage element of any device, flip-flop designing with low-power consumption is a very critical issue. In this paper, the design of double-edge-triggered (DET) flip-flop belonging to C-element using LECTOR technique is presented. As technology is scaling down continuously so leakage power is an important parameter on which circuit performance mainly depends, in this paper an improvement has been done by introducing effective arrangement of extra transistors in the conventional design. The conventional design and modified circuit are implemented at 45 nm CMOS technology using cadence virtuoso tool at different supply voltage varying from 0.7 to 1.1 V, and reduction in power consumption and improvement in the power delay product (PDP) is achieved as compared with the conventional design.
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