Analysis of Leakage Power Reduction Using LECTOR and ONOFIC Technique in Clock Gated Flip-Flop

Abstract

Clock gating is a common approach for minimizing dynamic power dissipation in synchronous circuits, and it can also assist in reducing the amount of power wasted by digital circuits. The system clock signal consumes the most power in an electronics product since it is responsible for component transition states, which often results in switching power consumption. Different ways of reducing leakage power in digital CMOS circuitry are described in this paper. ONOFIC and LECTOR techniques are used in D Flip-Flops (Transmission gate and C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS) to reduce leakage power. Digital circuits with optimized transistor sizing based on Logical Effort Theory (LE theory) have been implemented for high performance. The above-mentioned circuits are compared in terms of average power, delay, leakage power, and power- delay product (PDP). Circuit simulations are carried out in LTSpice with 65nm PTM technology with a 0.9V power supply.